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author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:38:18 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:38:18 +0300 |
commit | 0b4b42da734c1164b65a334351274f946b2d4dcb (patch) | |
tree | 5c4fc8a8b09ca962aa4335577fe3cf3a66ffcaff /rtl/modexpng_sdp_36k_x32_x16_wrapper.v | |
parent | 71f70252dfc7e41103dde420a721be8aa48486d5 (diff) |
Redesigned storage modules, added top-level module, added I/O storage space.
Diffstat (limited to 'rtl/modexpng_sdp_36k_x32_x16_wrapper.v')
-rw-r--r-- | rtl/modexpng_sdp_36k_x32_x16_wrapper.v | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/rtl/modexpng_sdp_36k_x32_x16_wrapper.v b/rtl/modexpng_sdp_36k_x32_x16_wrapper.v new file mode 100644 index 0000000..ff86802 --- /dev/null +++ b/rtl/modexpng_sdp_36k_x32_x16_wrapper.v @@ -0,0 +1,73 @@ +module modexpng_sdp_36k_x32_x16_wrapper +( + clk, clk_bus, + + ena, wea, + addra, dina, + + enb, + addrb, doutb +); + + + // + // Headers + // + `include "modexpng_parameters.vh" + + + // + // Ports + // + input clk; + input clk_bus; + + input ena; + input wea; + input [BANK_ADDR_W + OP_ADDR_W -1:0] addra; + input [ WORD_W -1:0] dina; + + input enb; + input [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addrb; + output [ BUS_DATA_W -1:0] doutb; + + + // + // BRAM_SDP_MACRO + // + BRAM_SDP_MACRO # + ( + .DEVICE ("7SERIES"), + + .BRAM_SIZE ("36Kb"), + + .WRITE_WIDTH (WORD_W), + .READ_WIDTH (BUS_DATA_W), + + .DO_REG (0), + .WRITE_MODE ("READ_FIRST"), + + .SRVAL (72'h000000000000000000), + .INIT (72'h000000000000000000), + + .INIT_FILE ("NONE"), + .SIM_COLLISION_CHECK ("NONE") + ) + BRAM_SDP_MACRO_inst + ( + .RST (1'b0), + + .WRCLK (clk), + .WREN (ena), + .WE ({2{wea}}), + .WRADDR (addra), + .DI (dina), + + .RDCLK (clk_bus), + .RDEN (enb), + .REGCE (1'b0), + .RDADDR (addrb), + .DO (doutb) + ); + +endmodule |