diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
| commit | 72902f5b40ac695786f5103d2a5a456c6c7ee83f (patch) | |
| tree | 59a644e74fa4fdc25c92b8d261150ef4899323f5 /rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v | |
| parent | 9eac252242c69e51a38a9a88c87b564dd40b6257 (diff) | |
Redesigned the testbench. Core clock does not necessarily need to be twice
faster than the bus clock now. It can be the same, or say four times faster.
Diffstat (limited to 'rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v')
| -rw-r--r-- | rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v | 59 |
1 files changed, 26 insertions, 33 deletions
diff --git a/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v b/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v index c74daac..586cadf 100644 --- a/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v +++ b/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v @@ -33,41 +33,34 @@ module modexpng_sdp_36k_x32_x16_wrapper_generic // - // BRAM_SDP_MACRO + // Memory // - BRAM_SDP_MACRO # - ( - .DEVICE ("7SERIES"), - - .BRAM_SIZE ("36Kb"), - - .WRITE_WIDTH (WORD_W), - .READ_WIDTH (BUS_DATA_W), - - .DO_REG (0), - .WRITE_MODE ("READ_FIRST"), - - .SRVAL (72'h000000000000000000), - .INIT (72'h000000000000000000), - - .INIT_FILE ("NONE"), - .SIM_COLLISION_CHECK ("NONE") - ) - BRAM_SDP_MACRO_inst - ( - .RST (1'b0), + reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1]; + + // + // Write Port + // + wire [BANK_ADDR_W + BUS_OP_ADDR_W -2:0] addra_msb = addra[BANK_ADDR_W + BUS_OP_ADDR_W -1:1]; + wire addra_lsb = addra[0]; + + always @(posedge clk) + // + if (ena && wea) begin + if (addra_lsb) mem[addra_msb][BUS_DATA_W-1:WORD_W] <= dina; + else mem[addra_msb][ WORD_W-1: 0] <= dina; + end + + // + // Read Port + // + reg [BUS_DATA_W -1:0] doutb_reg; - .WRCLK (clk), - .WREN (ena), - .WE ({2{wea}}), - .WRADDR (addra), - .DI (dina), + assign doutb = doutb_reg; - .RDCLK (clk_bus), - .RDEN (enb), - .REGCE (1'b0), - .RDADDR (addrb), - .DO (doutb) - ); + always @(posedge clk_bus) + // + if (enb) + doutb_reg <= mem[addrb]; + endmodule |