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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 02:05:02 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 02:05:02 +0300 |
| commit | 1fd8037d41be46d24b3610c89f781fe85def4317 (patch) | |
| tree | e407d6148e362bb3f24b46e634bd0ca01814b195 /src/tb/tb_factor.v | |
| parent | 52675d5fa64a1157fe85e041914179309eb2ed9e (diff) | |
Finished modulus-dependent coefficient calculation module:
* fixed bug with latency compensation
* cleaned up Verilog source
* added 512-bit testbench
* works in simulator
* synthesizes without warnings
Changes:
* made latency of generic processing element configurable
Diffstat (limited to 'src/tb/tb_factor.v')
| -rw-r--r-- | src/tb/tb_factor.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v index 53e6769..946883c 100644 --- a/src/tb/tb_factor.v +++ b/src/tb/tb_factor.v @@ -43,7 +43,7 @@ module tb_factor; //
// Test Vectors
//
- `include "../modexp_fpga_model_vectors.v";
+ `include "modexp_fpga_model_vectors.v";
//
// Parameters
|