aboutsummaryrefslogtreecommitdiff
path: root/src/tb/tb_factor.v
blob: 53e67698ccca55199df9a28109a0b991546f8c44 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
//======================================================================
//
// tb_factor.v
// -----------------------------------------------------------------------------
// Testbench for Montgomery factor calculation block.
//
// Authors: Pavel Shatov
//
// Copyright (c) 2017, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

`timescale 1ns / 1ps

module tb_factor;

		//
		// Test Vectors
		//
	`include "../modexp_fpga_model_vectors.v";
	
		//
		// Parameters
		//
	localparam NUM_WORDS_384 = 384 / 32;
		
		//
		// Clock (100 MHz)
		//
	reg clk = 1'b0;
	always #5 clk = ~clk;
			
		//
		// Inputs
		//
	reg				rst_n;
	reg				ena;
	
	reg	[ 3: 0]	n_num_words;

		//
		// Outputs
		//
	wire				rdy;

		//
		// Integers
		//
	integer w;
	
		//
		// BRAM Interfaces
		//
	wire	[ 3: 0]	core_n_addr;
	wire	[ 3: 0]	core_f_addr;
	
	wire	[31: 0]	core_n_data;
	wire	[31: 0]	core_f_data_in;

	wire				core_f_wren;

	reg	[ 3: 0]	tb_n_addr;
	reg	[ 3: 0]	tb_f_addr;

	reg	[31:0]	tb_n_data;
	wire	[31:0]	tb_f_data;
	
	reg				tb_n_wren;
	
		//
		// BRAMs
		//
	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
	bram_n (.clk(clk),
		.a_addr(tb_n_addr), .a_wr(tb_n_wren), .a_in(tb_n_data), .a_out(),
		.b_addr(core_n_addr), .b_out(core_n_data));

	bram_1rw_1ro_readfirst #(.MEM_WIDTH(32), .MEM_ADDR_BITS(4))
	bram_f (.clk(clk),
		.a_addr(core_f_addr), .a_wr(core_f_wren), .a_in(core_f_data_in), .a_out(),
		.b_addr(tb_f_addr), .b_out(tb_f_data));

		//
		// UUT
		//
	modexpa7_factor #
	(
		.OPERAND_ADDR_WIDTH		(4)	// 32 * (2**4) = 512-bit operands
	)
	uut
	(
		.clk				(clk), 
		.rst_n			(rst_n), 
		
		.ena				(ena), 
		.rdy				(rdy), 
		
		.n_bram_addr	(core_n_addr), 
		.f_bram_addr	(core_f_addr), 

		.n_bram_out		(core_n_data), 
		
		.f_bram_in		(core_f_data_in), 
		.f_bram_wr		(core_f_wren), 
		
		.n_num_words	(n_num_words)
	);


		//
		// Script
		//
	initial begin

		rst_n = 1'b0;
		ena = 1'b0;
		
		#200;		
		rst_n = 1'b1;
		#100;
		
		test_factor_384(N_384);
		
	end
      
		
		//
		// Test Tasks
		//
		
	task test_factor_384;
		input	[383:0] n;
		reg	[383:0] f;
		reg	[383:0] factor;
		integer i;
		begin
						
			calc_factor_384(n, f);							// calculate factor on-the-fly
			
				// make sure, that the value matches the one saved in the include file
			if (f !== FACTOR_384) begin
				$display("ERROR: Calculated factor value differs from the one in the test vector!");
				$finish;
			end
			
			
			n_num_words = 4'd11;								// set number of words
			
			write_memory_384(n);								// fill memory
			
			ena = 1;												// start operation
			#10;													//
			ena = 0;												// clear flag
			
			while (!rdy) #10;									// wait for operation to complete
			read_memory_384(factor);						// get result from memory
							
			$display("    calculated: %x", factor);	//
			$display("    expected:   %x", f);			//
							
				// check calculated value
			if (f === factor) begin
				$display("        OK");
				$display("SUCCESS: Test passed.");
			end else begin
				$display("        ERROR");
				$display("FAILURE: Test not passed.");
			end
		
		end
	
	endtask


	task write_memory_384;

		input	[383:0] n;

		reg	[383:0] n_shreg;
		
		begin
			
			tb_n_wren	= 1;														// start filling memories
			
			n_shreg       = n;													//
			
			for (w=0; w<NUM_WORDS_384; w=w+1) begin						// write all words
				
				tb_n_addr	= w[3:0];											// set addresses
				
				tb_n_data       = n_shreg[31:0];								//
				
				n_shreg       = {{32{1'bX}}, n_shreg[383:32]};			//
				
				#10;																	// wait for 1 clock tick
				
			end
			
			tb_n_addr	= {4{1'bX}};											// wipe addresses
			
			tb_n_data       = {32{1'bX}};										//
			
			tb_n_wren = 0;														// stop filling memories
		
		end
		
	endtask
			

	task read_memory_384;
	
		output	[383:0] f;
		reg		[383:0] f_shreg;
		
		begin
		
				// read result word-by-word
			for (w=0; w<NUM_WORDS_384; w=w+1) begin
				tb_f_addr	= w[3:0];							// set address
				#10;													// wait for 1 clock tick
				f_shreg = {tb_f_data, f_shreg[383:32]};	// store data word
			end
			
			tb_f_addr = {4{1'bX}};								// wipe address
			f = f_shreg;											// return
			
		end
		
	endtask


	task calc_factor_384;

		input		[383:0] n;
		output	[383:0] factor;
		reg		[383:0] f;
		reg		[384:0] f1;
		reg		[384:0] f2;
		integer i;

		begin

			f = 384'd1;

			for (i=0; i<768; i=i+1) begin
				f1 = {f, 1'b0};
				f2 = f1 - {1'b0, n};
				f = (f1 >= {1'b0, n}) ? f2 : f1;
			end

			factor = f;

		end

	endtask


endmodule

//======================================================================
// End of file
//======================================================================