Finished modulus-dependent coefficient calculation module:

 * fixed bug with latency compensation
 * cleaned up Verilog source
 * added 512-bit testbench
 * works in simulator
 * synthesizes without warnings

Changes:
 * made latency of generic processing element configurable

3 files changed, 186 insertions, 53 deletions

diff --git a/src/tb/tb_factor.v b/src/tb/tb_factor.v
index 53e6769..946883c 100644
--- a/src/tb/tb_factor.v
+++ b/src/tb/tb_factor.v
@@ -43,7 +43,7 @@ module tb_factor;
 		//

 		// Test Vectors

 		//

-	`include "../modexp_fpga_model_vectors.v";

+	`include "modexp_fpga_model_vectors.v";

 	

 		//

 		// Parameters

diff --git a/src/tb/tb_n_coeff.v b/src/tb/tb_n_coeff.v
index 6ab824a..269dc39 100644
--- a/src/tb/tb_n_coeff.v
+++ b/src/tb/tb_n_coeff.v
@@ -43,12 +43,13 @@ module tb_n_coeff;
 		//

 		// Test Vectors

 		//

-	`include "../modexp_fpga_model_vectors.v";

+	`include "modexp_fpga_model_vectors.v";

 	

 		//

 		// Parameters

 		//

 	localparam NUM_WORDS_384 = 384 / 32;

+	localparam NUM_WORDS_512 = 512 / 32;

 		

 		//

 		// Clock (100 MHz)

@@ -146,6 +147,7 @@ module tb_n_coeff;
 		#100;

 		

 		test_n_coeff_384(N_384);

+		test_n_coeff_512(N_512);

 		

 	end

       

@@ -169,9 +171,7 @@ module tb_n_coeff;
 				$finish;

 			end

 			

-			

-			n_num_words = 4'd11;								// set number of words
-			

+			n_num_words = 4'd11;								// set number of words	

 			write_memory_384(n);								// fill memory

 			
 			ena = 1;												// start operation
@@ -181,7 +181,7 @@ module tb_n_coeff;
 			while (!rdy) #10;									// wait for operation to complete

 			read_memory_384(result);						// get result from memory
 							

-			$display("    calculated: %x", result);	//

+			$display("    calculated: %x", result);	// display results

 			$display("    expected:   %x", n_coeff);	//

 							

 				// check calculated value

@@ -198,65 +198,159 @@ module tb_n_coeff;
 	endtask
 

 

-	task write_memory_384;

+	task test_n_coeff_512;
+		input	[511:0] n;

+		reg	[511:0] n_coeff;

+		reg	[511:0] result;

+		integer i;
+		begin

+						

+			calc_n_coeff_512(n, n_coeff);					// calculate n_coeff on-the-fly

+						

+				// make sure, that the value matches the one saved in the include file

+			if (n_coeff !== N_COEFF_512) begin

+				$display("ERROR: Calculated factor value differs from the one in the test vector!");

+				$finish;

+			end

+			

+			n_num_words = 4'd15;								// set number of words	

+			write_memory_512(n);								// fill memory

+			
+			ena = 1;												// start operation
+			#10;													//

+			ena = 0;												// clear flag

+			
+			while (!rdy) #10;									// wait for operation to complete

+			read_memory_512(result);						// get result from memory
+							

+			$display("    calculated: %x", result);	// display results

+			$display("    expected:   %x", n_coeff);	//

+							

+				// check calculated value

+			if (n_coeff === result) begin
+				$display("        OK");

+				$display("SUCCESS: Test passed.");
+			end else begin

+				$display("        ERROR");

+				$display("FAILURE: Test not passed.");

+			end

+		

+		end
+	

+	endtask
 

-		input	[383:0] n;

 

+		//

+		// write_memory_384

+		//

+	task write_memory_384;

+		//

+		input	[383:0] n;

 		reg	[383:0] n_shreg;

-		

+		//

 		begin
-			

-			tb_n_wren	= 1;														// start filling memories
-			
-			n_shreg       = n;													//

-			
-			for (w=0; w<NUM_WORDS_384; w=w+1) begin						// write all words
-				
-				tb_n_addr	= w[3:0];											// set addresses
-				
-				tb_n_data       = n_shreg[31:0];								//

-				
-				n_shreg       = {{32{1'bX}}, n_shreg[383:32]};			//

-				
-				#10;																	// wait for 1 clock tick
-				
+			//

+			tb_n_wren = 1;											// start filling memory
+			n_shreg = n;											// preset shift register

+			//
+			for (w=0; w<NUM_WORDS_384; w=w+1) begin		// write all words
+				tb_n_addr = w[3:0];								// set address
+				tb_n_data = n_shreg[31:0];						// set data
+				n_shreg = {{32{1'bX}}, n_shreg[383:32]};	// update shift register
+				#10;													// wait for 1 clock tick
 			end
-			
-			tb_n_addr	= {4{1'bX}};											// wipe addresses
-			
-			tb_n_data       = {32{1'bX}};										//

-			
-			tb_n_wren = 0;														// stop filling memories

-		

+			//
+			tb_n_addr = {4{1'bX}};								// wipe address
+			tb_n_data = {32{1'bX}};								// wipe data
+			tb_n_wren = 0;											// stop filling memory

+			//

 		end

-		

+		//

 	endtask
 			
 

+		//

+		// write_memory_512

+		//

+	task write_memory_512;

+		//

+		input	[511:0] n;

+		reg	[511:0] n_shreg;

+		//

+		begin
+			//

+			tb_n_wren = 1;											// start filling memory
+			n_shreg = n;											// preset shift register

+			//
+			for (w=0; w<NUM_WORDS_512; w=w+1) begin		// write all words
+				tb_n_addr = w[3:0];								// set address
+				tb_n_data = n_shreg[31:0];						// set data
+				n_shreg = {{32{1'bX}}, n_shreg[511:32]};	// update shift register
+				#10;													// wait for 1 clock tick
+			end
+			//
+			tb_n_addr = {4{1'bX}};								// wipe address
+			tb_n_data = {32{1'bX}};								// wipe data
+			tb_n_wren = 0;											// stop filling memory

+			//

+		end

+		//

+	endtask
+

+

+		//

+		// read_memory_384 

+		//

 	task read_memory_384;

-	

+		//

 		output	[383:0] n_coeff;

 		reg		[383:0] n_coeff_shreg;

-		

+		//

 		begin

-		

-				// read result word-by-word

-			for (w=0; w<NUM_WORDS_384; w=w+1) begin
-				tb_n_coeff_addr	= w[3:0];					// set address
-				#10;													// wait for 1 clock tick
+			//

+			for (w=0; w<NUM_WORDS_384; w=w+1) begin								// read result word-by-word
+				tb_n_coeff_addr	= w[3:0];											// set address
+				#10;																			// wait for 1 clock tick
 				n_coeff_shreg = {tb_n_coeff_data, n_coeff_shreg[383:32]};	// store data word
 			end

-			

-			tb_n_coeff_addr = {4{1'bX}};								// wipe address

-			n_coeff = n_coeff_shreg;											// return

-			

+			//

+			tb_n_coeff_addr = {4{1'bX}};												// wipe address

+			n_coeff = n_coeff_shreg;													// return

+			//

 		end

-		

+		//

 	endtask
 

 

-	task calc_n_coeff_384;

+		//

+		// read_memory_512

+		//

+	task read_memory_512;

+		//

+		output	[511:0] n_coeff;

+		reg		[511:0] n_coeff_shreg;

+		//

+		begin

+			//

+			for (w=0; w<NUM_WORDS_512; w=w+1) begin								// read result word-by-word
+				tb_n_coeff_addr	= w[3:0];											// set address
+				#10;																			// wait for 1 clock tick
+				n_coeff_shreg = {tb_n_coeff_data, n_coeff_shreg[511:32]};	// store data word
+			end

+			//

+			tb_n_coeff_addr = {4{1'bX}};												// wipe address

+			n_coeff = n_coeff_shreg;													// return

+			//

+		end

+		//

+	endtask

 

+

+		//

+		// calc_n_coeff_384

+		//

+	task calc_n_coeff_384;

+		//

 		input		[383:0] n;

 		output	[383:0] n_coeff;

 		reg		[383:0] r;

@@ -264,24 +358,63 @@ module tb_n_coeff;
 		reg		[383:0] t;

 		reg		[383:0] b;

 		integer i;

-

+		//

 		begin

-

-			r = 384'd1;

-			b = 384'd1;

+			//

+			r  = 384'd1;

+			b  = 384'd1;

 			nn = ~n + 1'b1;

-

+			//

 			for (i=1; i<384; i=i+1) begin

+				//

 				b = {b[382:0], 1'b0};

 				t = r * nn;

+				//

 				if (t[i] == 1'b1)

 					r = r + b;

+				//

 			end

-

+			//

 			n_coeff = r;

-

+			//

 		end

+		//

+	endtask
+

 

+		//

+		// calc_n_coeff_512

+		//

+	task calc_n_coeff_512;

+		//

+		input		[511:0] n;

+		output	[511:0] n_coeff;

+		reg		[511:0] r;

+		reg		[511:0] nn;

+		reg		[511:0] t;

+		reg		[511:0] b;

+		integer i;

+		//

+		begin

+			//

+			r  = 512'd1;

+			b  = 512'd1;

+			nn = ~n + 1'b1;

+			//

+			for (i=1; i<512; i=i+1) begin

+				//

+				b = {b[510:0], 1'b0};

+				t = r * nn;

+				//

+				if (t[i] == 1'b1)

+					r = r + b;

+				//

+			end

+			//

+			n_coeff = r;

+			//

+		end

+		//

 	endtask
 

 

diff --git a/src/tb/tb_systolic_multiplier.v b/src/tb/tb_systolic_multiplier.v
index 3cbb8d1..a6380e5 100644
--- a/src/tb/tb_systolic_multiplier.v
+++ b/src/tb/tb_systolic_multiplier.v
@@ -44,7 +44,7 @@ module tb_systolic_multiplier;
 		//

 		// Test Vectors

 		//

-	`include "../modexp_fpga_model_vectors.v";

+	`include "modexp_fpga_model_vectors.v";

 	

 	

 		//