diff options
author | Rob Austein <sra@hactrn.net> | 2017-03-07 19:46:44 -0500 |
---|---|---|
committer | Rob Austein <sra@hactrn.net> | 2017-03-07 19:46:44 -0500 |
commit | ab4638f70ee846de7398a3d78d467a9551e508cf (patch) | |
tree | 61c330bb0be48daa4faf3830abfa84c9e5f400d7 /rtl/lowlevel/generic/adder32_generic.v | |
parent | 9fa6e368879d30835880b3bb0e87c8cf13dd9874 (diff) |
Promote code common to both ECDSA* cores to separate repository in core/ tree.
Pavel's two ECDSA base point multiplier cores share a fair amount of
code. Maintenance issues aside, the duplication confused the Xilinx
synthesis tools if one tried to build a single bitstream containing
both cores, so we've separated the common code out into this library.
The selection of files in this library was done by comparing the rtl
trees of the two original core repositories using "diff -rqws" and
selecting the files which diff reported as being identical.
Also dealt with some cosmetic issues (indentation, Windows-isms, etc).
Diffstat (limited to 'rtl/lowlevel/generic/adder32_generic.v')
-rw-r--r-- | rtl/lowlevel/generic/adder32_generic.v | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/rtl/lowlevel/generic/adder32_generic.v b/rtl/lowlevel/generic/adder32_generic.v index b9c94aa..eadfb6f 100644 --- a/rtl/lowlevel/generic/adder32_generic.v +++ b/rtl/lowlevel/generic/adder32_generic.v @@ -2,7 +2,7 @@ // // adder32_generic.v // ----------------------------------------------------------------------------- -// Generic 32-bit adder.
+// Generic 32-bit adder. // // Authors: Pavel Shatov // @@ -34,34 +34,34 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -//------------------------------------------------------------------------------
-
-module adder32_generic
- (
- input clk, // clock
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
- - // - // Sum - // - reg [32: 0] s_int;
-
- always @(posedge clk)
- s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
-
- //
- // Output
- //
- assign s = s_int[31:0];
- assign c_out = s_int[32];
-
-endmodule
-
+//------------------------------------------------------------------------------ + +module adder32_generic + ( + input clk, // clock + input [31: 0] a, // operand input + input [31: 0] b, // operand input + output [31: 0] s, // sum output + input c_in, // carry input + output c_out // carry output + ); + + // + // Sum + // + reg [32: 0] s_int; + + always @(posedge clk) + s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in}; + + // + // Output + // + assign s = s_int[31:0]; + assign c_out = s_int[32]; + +endmodule + //------------------------------------------------------------------------------ // End-of-File -//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------ |