Promote code common to both ECDSA* cores to separate repository in core/ tree.

Pavel's two ECDSA base point multiplier cores share a fair amount of
code.  Maintenance issues aside, the duplication confused the Xilinx
synthesis tools if one tried to build a single bitstream containing
both cores, so we've separated the common code out into this library.

The selection of files in this library was done by comparing the rtl
trees of the two original core repositories using "diff -rqws" and
selecting the files which diff reported as being identical.

Also dealt with some cosmetic issues (indentation, Windows-isms, etc).

4 files changed, 161 insertions, 161 deletions

diff --git a/rtl/lowlevel/generic/adder32_generic.v b/rtl/lowlevel/generic/adder32_generic.v
index b9c94aa..eadfb6f 100644
--- a/rtl/lowlevel/generic/adder32_generic.v
+++ b/rtl/lowlevel/generic/adder32_generic.v
@@ -2,7 +2,7 @@
 //
 // adder32_generic.v
 // -----------------------------------------------------------------------------
-// Generic 32-bit adder.

+// Generic 32-bit adder.
 //
 // Authors: Pavel Shatov
 //
@@ -34,34 +34,34 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 //
-//------------------------------------------------------------------------------

-

-module adder32_generic

-	(

-		input					clk,		// clock

-		input		[31: 0]	a,			// operand input

-		input		[31: 0]	b,			// operand input

-		output	[31: 0]	s,			// sum output

-		input					c_in,		// carry input

-		output				c_out		// carry output

-	);

-	
-		//
-		// Sum
-		//
-	reg	[32: 0]	s_int;

-	

-	always @(posedge clk)

-		s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};

-		

-		//

-		// Output

-		//

-	assign s = s_int[31:0];

-	assign c_out = s_int[32];

-		

-endmodule

-

+//------------------------------------------------------------------------------
+
+module adder32_generic
+  (
+   input 	  clk, // clock
+   input [31: 0]  a, // operand input
+   input [31: 0]  b, // operand input
+   output [31: 0] s, // sum output
+   input 	  c_in, // carry input
+   output 	  c_out		// carry output
+   );
+
+   //
+   // Sum
+   //
+   reg [32: 0] 	  s_int;
+
+   always @(posedge clk)
+     s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
+
+   //
+   // Output
+   //
+   assign s = s_int[31:0];
+   assign c_out = s_int[32];
+
+endmodule
+
 //------------------------------------------------------------------------------
 // End-of-File
-//------------------------------------------------------------------------------

+//------------------------------------------------------------------------------
diff --git a/rtl/lowlevel/generic/adder47_generic.v b/rtl/lowlevel/generic/adder47_generic.v
index f472061..406c175 100644
--- a/rtl/lowlevel/generic/adder47_generic.v
+++ b/rtl/lowlevel/generic/adder47_generic.v
@@ -2,7 +2,7 @@
 //
 // adder47_generic.v
 // -----------------------------------------------------------------------------
-// Generic 47-bit adder.

+// Generic 47-bit adder.
 //
 // Authors: Pavel Shatov
 //
@@ -34,31 +34,31 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 //
-//------------------------------------------------------------------------------

-

-module adder47_generic

-	(

-		input					clk,		// clock

-		input		[46: 0]	a,			// operand input

-		input		[46: 0]	b,			// operand input

-		output	[46: 0]	s			// sum output

-	);

-	

-		//
-		// Sum
-		//
-	reg	[46: 0]	s_int;

-	

-	always @(posedge clk)

-		s_int <= a + b;

-		

-		//

-		// Output

-		//

-	assign s = s_int;

-

-endmodule

-

+//------------------------------------------------------------------------------
+
+module adder47_generic
+  (
+   input 	  clk, // clock
+   input [46: 0]  a, // operand input
+   input [46: 0]  b, // operand input
+   output [46: 0] s			// sum output
+   );
+
+   //
+   // Sum
+   //
+   reg [46: 0] 	  s_int;
+
+   always @(posedge clk)
+     s_int <= a + b;
+
+   //
+   // Output
+   //
+   assign s = s_int;
+
+endmodule
+
 //------------------------------------------------------------------------------
 // End-of-File
-//------------------------------------------------------------------------------

+//------------------------------------------------------------------------------
diff --git a/rtl/lowlevel/generic/mac16_generic.v b/rtl/lowlevel/generic/mac16_generic.v
index dc95645..6d120a3 100644
--- a/rtl/lowlevel/generic/mac16_generic.v
+++ b/rtl/lowlevel/generic/mac16_generic.v
@@ -2,7 +2,7 @@
 //
 // mac16_generic.v
 // -----------------------------------------------------------------------------
-// Generic 16-bit multiplier and 47-bit accumulator.

+// Generic 16-bit multiplier and 47-bit accumulator.
 //
 // Authors: Pavel Shatov
 //
@@ -34,41 +34,41 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 //
-//------------------------------------------------------------------------------

-

-module mac16_generic

-	(

-		input					clk,		// clock

-		input					clr,		// clear accumulator (active-high)

-		input					ce,		// enable clock (active-high)

-		input		[15: 0]	a,			// operand input

-		input		[15: 0]	b,			// operand input

-		output	[46: 0]	s			// sum output

-	);

-	

-		//

-		// Multiplier

-		//

-	wire	[31: 0]	p = {{16{1'b0}}, a} * {{16{1'b0}}, b};

-	wire	[46: 0]	p_ext = {{15{1'b0}}, p};

-		

-		//

-		// Accumulator

-		//

-	reg	[46: 0]	s_int;

-	

-	always @(posedge clk)

-		//

-		if (ce) s_int <= clr ? p_ext : p_ext + s_int;

-		

-		//

-		// Output

-		//

-	assign s = s_int;

-

-endmodule

-

-

+//------------------------------------------------------------------------------
+
+module mac16_generic
+  (
+   input 	  clk, // clock
+   input 	  clr, // clear accumulator (active-high)
+   input 	  ce, // enable clock (active-high)
+   input [15: 0]  a, // operand input
+   input [15: 0]  b, // operand input
+   output [46: 0] s			// sum output
+   );
+
+   //
+   // Multiplier
+   //
+   wire [31: 0]   p = {{16{1'b0}}, a} * {{16{1'b0}}, b};
+   wire [46: 0]   p_ext = {{15{1'b0}}, p};
+
+   //
+   // Accumulator
+   //
+   reg [46: 0] 	  s_int;
+
+   always @(posedge clk)
+     //
+     if (ce) s_int <= clr ? p_ext : p_ext + s_int;
+
+   //
+   // Output
+   //
+   assign s = s_int;
+
+endmodule
+
+
 //------------------------------------------------------------------------------
 // End-of-File
-//------------------------------------------------------------------------------

+//------------------------------------------------------------------------------
diff --git a/rtl/lowlevel/generic/subtractor32_generic.v b/rtl/lowlevel/generic/subtractor32_generic.v
index 46aefe8..5137ace 100644
--- a/rtl/lowlevel/generic/subtractor32_generic.v
+++ b/rtl/lowlevel/generic/subtractor32_generic.v
@@ -1,67 +1,67 @@
-//------------------------------------------------------------------------------

-//

-// subtractor32_generic.v

-// -----------------------------------------------------------------------------

-// Generic 32-bit subtractor.

-//

-// Authors: Pavel Shatov

-//

-// Copyright (c) 2016, NORDUnet A/S

-//

-// Redistribution and use in source and binary forms, with or without

-// modification, are permitted provided that the following conditions are met:

-//

-// - Redistributions of source code must retain the above copyright notice,

-//   this list of conditions and the following disclaimer.

-//

-// - Redistributions in binary form must reproduce the above copyright notice,

-//   this list of conditions and the following disclaimer in the documentation

-//   and/or other materials provided with the distribution.

-//

-// - Neither the name of the NORDUnet nor the names of its contributors may be

-//   used to endorse or promote products derived from this software without

-//   specific prior written permission.

-//

-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-// POSSIBILITY OF SUCH DAMAGE.

-//

-//------------------------------------------------------------------------------

-

-module subtractor32_generic

-	(

-		input					clk,

-		input		[31: 0]	a,

-		input		[31: 0]	b,

-		output	[31: 0]	d,

-		input					b_in,

-		output				b_out	

-	);

-

-		//
-		// Difference
-		//
-	reg	[32: 0]	d_int;

-	

-	always @(posedge clk)

-		d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in};

-		

-		//

-		// Output

-		//

-	assign d = d_int[31:0];

-	assign b_out = d_int[32];

-

-endmodule

-

-//------------------------------------------------------------------------------

-// End-of-File

-//------------------------------------------------------------------------------

+//------------------------------------------------------------------------------
+//
+// subtractor32_generic.v
+// -----------------------------------------------------------------------------
+// Generic 32-bit subtractor.
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2016, NORDUnet A/S
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may be
+//   used to endorse or promote products derived from this software without
+//   specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//------------------------------------------------------------------------------
+
+module subtractor32_generic
+  (
+   input 	  clk,
+   input [31: 0]  a,
+   input [31: 0]  b,
+   output [31: 0] d,
+   input 	  b_in,
+   output 	  b_out
+   );
+
+   //
+   // Difference
+   //
+   reg [32: 0] 	  d_int;
+
+   always @(posedge clk)
+     d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in};
+
+   //
+   // Output
+   //
+   assign d = d_int[31:0];
+   assign b_out = d_int[32];
+
+endmodule
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------