core/hash/sha256 - Verilog implementation of the SHA-256 cryptographic hash function

Age	Commit message (Expand)	Author
2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson
2014-03-16	Adding self resetting init and next flags. Updating TBs to not reset the flag...	Joachim Strömbergson
2014-03-15	(1) Updated interface to new std. (2) Added missing input designation in task...	Joachim Strömbergson
2014-02-26	Removed the positions of W no longer needed.	Joachim Strömbergson
2014-02-26	Changed the python model to use a sliding window for W.	Joachim Strömbergson
2014-02-23	Fixed compile problems due to copy crime.	Joachim Strömbergson
2014-02-23	Moved wmem update logic to a separate process.	Joachim Strömbergson
2014-02-22	Updated testbenches to the new sliding window W-mem.	Joachim Strömbergson
2014-02-22	Changed W-memory into sliding window. This also affected interface and integr...	Joachim Strömbergson
2014-02-19	Adding a Python model for the SHA256 core.	Joachim Strömbergson
2014-02-19	Adding a testbench for the Wishbone wrapper.	Joachim Strömbergson
2014-02-19	Adding a testbench for the SHA256 top level wrapper.	Joachim Strömbergson
2014-02-19	Adding a testbench for the SHA256 core.	Joachim Strömbergson
2014-02-19	Adding a testbench for the w memory module.	Joachim Strömbergson
2014-02-19	Adding a Wishbone wrapper for the SHA256 core.	Joachim Strömbergson
2014-02-19	Adding top level wrapper for the sha256. This wrapper provides a simple memor...	Joachim Strömbergson
2014-02-19	Source for the main part of the sha256 core.	Joachim Strömbergson
2014-02-19	Adding the W memory including scheduler and expansion functionality.	Joachim Strömbergson
2014-02-19	Adding K constant memory source file.	Joachim Strömbergson