(1) Updated interface to new std. (2) Added missing input designation in tasks. Now simumaltion with ModelSim works.

2 files changed, 83 insertions, 81 deletions

diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index 8f7f7b6..06ebd3d 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -7,7 +7,8 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
+// All rights reserved.
 // 
 // Redistribution and use in source and binary forms, with or 
 // without modification, are permitted provided that the following 
@@ -43,12 +44,12 @@ module sha256(
               
               // Control.
               input wire           cs,
-              input wire           write_read,
+              input wire           we,
               
               // Data ports.
               input wire  [7 : 0]  address,
-              input wire  [31 : 0] data_in,
-              output wire [31 : 0] data_out,
+              input wire  [31 : 0] write_data,
+              output wire [31 : 0] read_data,
               output wire          error
              );
 
@@ -155,7 +156,7 @@ module sha256(
   wire [255 : 0] core_digest;
   wire           core_digest_valid;
 
-  reg [31 : 0]   tmp_data_out;
+  reg [31 : 0]   tmp_read_data;
   reg            tmp_error;
   
   
@@ -171,8 +172,8 @@ module sha256(
                        block8_reg, block9_reg, block10_reg, block11_reg,
                        block12_reg, block13_reg, block14_reg, block15_reg};
 
-  assign data_out = tmp_data_out;
-  assign error    = tmp_error;
+  assign read_data = tmp_read_data;
+  assign error     = tmp_error;
   
              
   //----------------------------------------------------------------
@@ -234,8 +235,8 @@ module sha256(
 
           if (ctrl_we)
             begin
-              init_reg <= data_in[CTRL_INIT_BIT];
-              next_reg <= data_in[CTRL_NEXT_BIT];
+              init_reg <= write_data[CTRL_INIT_BIT];
+              next_reg <= write_data[CTRL_NEXT_BIT];
             end
           
           if (core_digest_valid)
@@ -245,82 +246,82 @@ module sha256(
 
           if (block0_we)
             begin
-              block0_reg <= data_in;
+              block0_reg <= write_data;
             end
 
           if (block1_we)
             begin
-              block1_reg <= data_in;
+              block1_reg <= write_data;
             end
 
           if (block2_we)
             begin
-              block2_reg <= data_in;
+              block2_reg <= write_data;
             end
 
           if (block3_we)
             begin
-              block3_reg <= data_in;
+              block3_reg <= write_data;
             end
 
           if (block4_we)
             begin
-              block4_reg <= data_in;
+              block4_reg <= write_data;
             end
 
           if (block5_we)
             begin
-              block5_reg <= data_in;
+              block5_reg <= write_data;
             end
 
           if (block6_we)
             begin
-              block6_reg <= data_in;
+              block6_reg <= write_data;
             end
 
           if (block7_we)
             begin
-              block7_reg <= data_in;
+              block7_reg <= write_data;
             end
 
           if (block8_we)
             begin
-              block8_reg <= data_in;
+              block8_reg <= write_data;
             end
 
           if (block9_we)
             begin
-              block9_reg <= data_in;
+              block9_reg <= write_data;
             end
 
           if (block10_we)
             begin
-              block10_reg <= data_in;
+              block10_reg <= write_data;
             end
 
           if (block11_we)
             begin
-              block11_reg <= data_in;
+              block11_reg <= write_data;
             end
 
           if (block12_we)
             begin
-              block12_reg <= data_in;
+              block12_reg <= write_data;
             end
 
           if (block13_we)
             begin
-              block13_reg <= data_in;
+              block13_reg <= write_data;
             end
 
           if (block14_we)
             begin
-              block14_reg <= data_in;
+              block14_reg <= write_data;
             end
 
           if (block15_we)
             begin
-              block15_reg <= data_in;
+              block15_reg <= write_data;
             end
           
         end
@@ -352,12 +353,12 @@ module sha256(
       block13_we   = 0;
       block14_we   = 0;
       block15_we   = 0;
-      tmp_data_out = 32'h00000000;
+      tmp_read_data = 32'h00000000;
       tmp_error    = 0;
       
       if (cs)
         begin
-          if (write_read)
+          if (we)
             begin
               case (address)
                 // Write operations.
@@ -451,7 +452,7 @@ module sha256(
                     tmp_error = 1;
                   end
               endcase // case (address)
-            end // if (write_read)
+            end // if (we)
 
           else
             begin
@@ -459,147 +460,147 @@ module sha256(
                 // Read operations.
                 ADDR_NAME0:
                   begin
-                    tmp_data_out = CORE_NAME0;
+                    tmp_read_data = CORE_NAME0;
                   end
 
                 ADDR_NAME1:
                   begin
-                    tmp_data_out = CORE_NAME1;
+                    tmp_read_data = CORE_NAME1;
                   end
                 
                 ADDR_VERSION:
                   begin
-                    tmp_data_out = CORE_VERSION;
+                    tmp_read_data = CORE_VERSION;
                   end
 
                 ADDR_CTRL:
                   begin
-                    tmp_data_out = {28'h0000000, 2'b00, next_reg, init_reg};
+                    tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg};
                   end
                 
                 ADDR_STATUS:
                   begin
-                    tmp_data_out = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
+                    tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
                   end
                 
                 ADDR_BLOCK0:
                   begin
-                    tmp_data_out = block0_reg;
+                    tmp_read_data = block0_reg;
                   end
 
                 ADDR_BLOCK1:
                   begin
-                    tmp_data_out = block1_reg;
+                    tmp_read_data = block1_reg;
                   end
 
                 ADDR_BLOCK2:
                   begin
-                    tmp_data_out = block2_reg;
+                    tmp_read_data = block2_reg;
                   end
 
                 ADDR_BLOCK3:
                   begin
-                    tmp_data_out = block3_reg;
+                    tmp_read_data = block3_reg;
                   end
 
                 ADDR_BLOCK4:
                   begin
-                    tmp_data_out = block4_reg;
+                    tmp_read_data = block4_reg;
                   end
 
                 ADDR_BLOCK5:
                   begin
-                    tmp_data_out = block5_reg;
+                    tmp_read_data = block5_reg;
                   end
 
                 ADDR_BLOCK6:
                   begin
-                    tmp_data_out = block6_reg;
+                    tmp_read_data = block6_reg;
                   end
 
                 ADDR_BLOCK7:
                   begin
-                    tmp_data_out = block7_reg;
+                    tmp_read_data = block7_reg;
                   end
 
                 ADDR_BLOCK8:
                   begin
-                    tmp_data_out = block8_reg;
+                    tmp_read_data = block8_reg;
                   end
 
                 ADDR_BLOCK9:
                   begin
-                    tmp_data_out = block9_reg;
+                    tmp_read_data = block9_reg;
                   end
 
                 ADDR_BLOCK10:
                   begin
-                    tmp_data_out = block10_reg;
+                    tmp_read_data = block10_reg;
                   end
 
                 ADDR_BLOCK11:
                   begin
-                    tmp_data_out = block11_reg;
+                    tmp_read_data = block11_reg;
                   end
 
                 ADDR_BLOCK12:
                   begin
-                    tmp_data_out = block12_reg;
+                    tmp_read_data = block12_reg;
                   end
 
                 ADDR_BLOCK13:
                   begin
-                    tmp_data_out = block13_reg;
+                    tmp_read_data = block13_reg;
                   end
 
                 ADDR_BLOCK14:
                   begin
-                    tmp_data_out = block14_reg;
+                    tmp_read_data = block14_reg;
                   end
 
                 ADDR_BLOCK15:
                   begin
-                    tmp_data_out = block15_reg;
+                    tmp_read_data = block15_reg;
                   end
 
                 ADDR_DIGEST0:
                   begin
-                    tmp_data_out = digest_reg[255 : 224];
+                    tmp_read_data = digest_reg[255 : 224];
                   end
 
                 ADDR_DIGEST1:
                   begin
-                    tmp_data_out = digest_reg[223 : 192];
+                    tmp_read_data = digest_reg[223 : 192];
                   end
 
                 ADDR_DIGEST2:
                   begin
-                    tmp_data_out = digest_reg[191 : 160];
+                    tmp_read_data = digest_reg[191 : 160];
                   end
 
                 ADDR_DIGEST3:
                   begin
-                    tmp_data_out = digest_reg[159 : 128];
+                    tmp_read_data = digest_reg[159 : 128];
                   end
 
                 ADDR_DIGEST4:
                   begin
-                    tmp_data_out = digest_reg[127 :  96];
+                    tmp_read_data = digest_reg[127 :  96];
                   end
 
                 ADDR_DIGEST5:
                   begin
-                    tmp_data_out = digest_reg[95  :  64];
+                    tmp_read_data = digest_reg[95  :  64];
                   end
 
                 ADDR_DIGEST6:
                   begin
-                    tmp_data_out = digest_reg[63  :  32];
+                    tmp_read_data = digest_reg[63  :  32];
                   end
 
                 ADDR_DIGEST7:
                   begin
-                    tmp_data_out = digest_reg[31  :   0];
+                    tmp_read_data = digest_reg[31  :   0];
                   end
                 
                 default:
diff --git a/src/tb/tb_sha256.v b/src/tb/tb_sha256.v
index eaee522..69f2186 100644
--- a/src/tb/tb_sha256.v
+++ b/src/tb/tb_sha256.v
@@ -7,6 +7,7 @@
 //
 // Author: Joachim Strombergson
 // Copyright (c) 2014, SUNET
+// All rights reserved.
 // 
 // Redistribution and use in source and binary forms, with or 
 // without modification, are permitted provided that the following 
@@ -103,10 +104,10 @@ module tb_sha256();
   reg           tb_clk;
   reg           tb_reset_n;
   reg           tb_cs;
-  reg           tb_write_read;
+  reg           tb_we;
   reg [7 : 0]   tb_address;
-  reg [31 : 0]  tb_data_in;
-  wire [31 : 0] tb_data_out;
+  reg [31 : 0]  tb_write_data;
+  wire [31 : 0] tb_read_data;
   wire          tb_error;
 
   reg [31 : 0]  read_data;
@@ -121,12 +122,12 @@ module tb_sha256();
              .reset_n(tb_reset_n),
              
              .cs(tb_cs),
-             .write_read(tb_write_read),
+             .we(tb_we),
              
              
              .address(tb_address),
-             .data_in(tb_data_in),
-             .data_out(tb_data_out),
+             .write_data(tb_write_data),
+             .read_data(tb_read_data),
              .error(tb_error)
             );
   
@@ -165,12 +166,12 @@ module tb_sha256();
       $display("State of DUT");
       $display("------------");
       $display("Inputs and outputs:");
-      $display("cs = 0x%01x, write_read = 0x%01x", 
-               dut.cs, dut.write_read);
+      $display("cs = 0x%01x, we = 0x%01x", 
+               dut.cs, dut.we);
       $display("address = 0x%02x", dut.address);
-      $display("data_in = 0x%08x, data_out = 0x%08x", 
-               dut.data_in, dut.data_out);
-      $display("tmp_data_out = 0x%08x", dut.tmp_data_out);
+      $display("write_data = 0x%08x, read_data = 0x%08x", 
+               dut.write_data, dut.read_data);
+      $display("tmp_read_data = 0x%08x", dut.tmp_read_data);
       $display("");
 
       $display("Control and status:");
@@ -229,9 +230,9 @@ module tb_sha256();
       tb_clk = 0;
       tb_reset_n = 0;
       tb_cs = 0;
-      tb_write_read = 0;
+      tb_we = 0;
       tb_address = 6'h00;
-      tb_data_in = 32'h00000000;
+      tb_write_data = 32'h00000000;
     end
   endtask // init_dut
 
@@ -293,12 +294,12 @@ module tb_sha256();
         end
          
       tb_address = address;
-      tb_data_in = word;
+      tb_write_data = word;
       tb_cs = 1;
-      tb_write_read = 1;
+      tb_we = 1;
       #(2 * CLK_HALF_PERIOD);
       tb_cs = 0;
-      tb_write_read = 0;
+      tb_we = 0;
     end
   endtask // write_word
 
@@ -341,9 +342,9 @@ module tb_sha256();
     begin
       tb_address = address;
       tb_cs = 1;
-      tb_write_read = 0;
+      tb_we = 0;
       #(2 * CLK_HALF_PERIOD);
-      read_data = tb_data_out;
+      read_data = tb_read_data;
       tb_cs = 0;
 
       if (DEBUG)
@@ -416,8 +417,8 @@ module tb_sha256();
   //
   // Perform test of a single block digest.
   //----------------------------------------------------------------
-  task single_block_test([511 : 0] block,
-                         [255 : 0] expected);
+  task single_block_test(input [511 : 0] block,
+                         input [255 : 0] expected);
     begin
       $display("*** TC%01d - Single block test started.", tc_ctr); 
      
@@ -451,10 +452,10 @@ module tb_sha256();
   // Perform test of a double block digest. Note that we check
   // the digests for both the first and final block.
   //----------------------------------------------------------------
-  task double_block_test([511 : 0] block0,
-                         [255 : 0] expected0,
-                         [511 : 0] block1,
-                         [255 : 0] expected1
+  task double_block_test(input [511 : 0] block0,
+                         input [255 : 0] expected0,
+                         input [511 : 0] block1,
+                         input [255 : 0] expected1
                         );
     begin
       $display("*** TC%01d - Double block test started.", tc_ctr);