Age | Commit message (Collapse) | Author | |
---|---|---|---|
2018-10-18 | Compacted the code for K constants. | Joachim Strömbergson | |
2018-10-18 | (1) Locked down API to ignore read or write requests that could leak info or ↵ | Joachim Strömbergson | |
cause incorrect behaviour during processing. (2) Cleaned up API registers and the API. | |||
2018-10-16 | Added width definition. | Joachim Strömbergson | |
2018-08-28 | Connected the pipeline regs for t1 and t2 in the stat update logic. Verified ↵ | Joachim Strömbergson | |
functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1. | |||
2018-08-28 | Added pipeline register and stall cycle in the FSM to accomodate the ↵ | Joachim Strömbergson | |
pipeline. Registers not yet used in the design. Cleaned up constants to silence lint. | |||
2018-04-27 | Removed FSM and cleaned up code in W mem. Cleaned up testbenches to silence ↵ | Joachim Strömbergson | |
warnings. | |||
2016-05-31 | Adding functionality to support both SHA224 and SHA256 digest modes. Note: ↵ | Joachim Strömbergson | |
This update changes the ADDR_CTRL API register since it adds a mode bit. The version major number has been bumped to reflect this API change. The top level testbench contains tests for SHA224 as well as old tests for SHA256. The core level tb still only tests SHA256. | |||
2016-05-31 | Fixed long constants and instead rely on zero extend in Verilog. | Joachim Strömbergson | |
2015-12-13 | whack copyrights | Paul Selkirk | |
2015-07-17 | Minor cleanup. | Joachim Strömbergson | |
2015-07-17 | Removed the address defines not needed. | Joachim Strömbergson | |
2015-07-17 | Since state is digest having separate addresses for writing state is ↵ | Joachim Strömbergson | |
superflous. Captain slow. | |||
2015-07-16 | Added logic to write state into the state registers. Simplified the state ↵ | Joachim Strömbergson | |
write interface to a common data port. | |||
2015-07-16 | The digest is the complete state so we only need to be able to write back ↵ | Joachim Strömbergson | |
state. The state addresses are still readable though. | |||
2015-07-16 | (1) Adding addresses to be able to read and write the internal hash state ↵ | Joachim Strömbergson | |
from the API. (2) Bumped version to reflect the changes to the API. (3) Added ports for state access in the core module and connected them in the top level wrapper. | |||
2015-03-31 | Revert streamlined wrapper, and don't delay register reads. | Paul Selkirk | |
2015-03-17 | Rearrange cores. | Paul Selkirk | |
2015-03-11 | Removed the wishbone wrapper we don't use. | Joachim Strömbergson | |
2014-11-07 | Changed to asynch reset. | Joachim Strömbergson | |
2014-11-06 | Fixed nits found using verilator linter. Removed trailing whitespace. | Joachim Strömbergson | |
2014-03-17 | Removed redundant flag reset wires. | Joachim Strömbergson | |
2014-03-16 | Adding self resetting init and next flags. Updating TBs to not reset the ↵ | Joachim Strömbergson | |
flags. Fixing clock parameter naming. | |||
2014-03-15 | (1) Updated interface to new std. (2) Added missing input designation in ↵ | Joachim Strömbergson | |
tasks. Now simumaltion with ModelSim works. | |||
2014-02-23 | Fixed compile problems due to copy crime. | Joachim Strömbergson | |
2014-02-23 | Moved wmem update logic to a separate process. | Joachim Strömbergson | |
2014-02-22 | Changed W-memory into sliding window. This also affected interface and ↵ | Joachim Strömbergson | |
integration in the core. | |||
2014-02-19 | Adding a Wishbone wrapper for the SHA256 core. | Joachim Strömbergson | |
2014-02-19 | Adding top level wrapper for the sha256. This wrapper provides a simple ↵ | Joachim Strömbergson | |
memory like interface. | |||
2014-02-19 | Source for the main part of the sha256 core. | Joachim Strömbergson | |
2014-02-19 | Adding the W memory including scheduler and expansion functionality. | Joachim Strömbergson | |
2014-02-19 | Adding K constant memory source file. | Joachim Strömbergson | |