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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-07-16 17:22:04 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-07-16 17:22:04 +0200
commit34693748aaa7b7d075ad98b69bc31eb722270786 (patch)
tree57c3814937c4f333af79be236b36604109bf2e52 /src/rtl
parent13c73ced97009e31abc7bf1740200e4e031f2fb7 (diff)
Added logic to write state into the state registers. Simplified the state write interface to a common data port.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha256.v32
-rw-r--r--src/rtl/sha256_core.v56
2 files changed, 42 insertions, 46 deletions
diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index 7f1dc94..5e733bd 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -213,29 +213,15 @@ module sha256(
.block(core_block),
// State access ports
- .H0_wr_data(write_data),
- .H0_we(state0_we),
-
- .H1_wr_data(write_data),
- .H1_we(state1_we),
-
- .H2_wr_data(write_data),
- .H2_we(state2_we),
-
- .H3_wr_data(write_data),
- .H3_we(state3_we),
-
- .H4_wr_data(write_data),
- .H4_we(state4_we),
-
- .H5_wr_data(write_data),
- .H5_we(state5_we),
-
- .H6_wr_data(write_data),
- .H6_we(state6_we),
-
- .H7_wr_data(write_data),
- .H7_we(state7_we),
+ .state_wr_data(write_data),
+ .state0_we(state0_we),
+ .state1_we(state1_we),
+ .state2_we(state2_we),
+ .state3_we(state3_we),
+ .state4_we(state4_we),
+ .state5_we(state5_we),
+ .state6_we(state6_we),
+ .state7_we(state7_we),
.ready(core_ready),
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index fa21862..3587a85 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -46,29 +46,15 @@ module sha256_core(
input wire [511 : 0] block,
// State access ports
- input wire [31 : 0] H0_wr_data,
- input wire H0_we,
-
- input wire [31 : 0] H1_wr_data,
- input wire H1_we,
-
- input wire [31 : 0] H2_wr_data,
- input wire H2_we,
-
- input wire [31 : 0] H3_wr_data,
- input wire H3_we,
-
- input wire [31 : 0] H4_wr_data,
- input wire H4_we,
-
- input wire [31 : 0] H5_wr_data,
- input wire H5_we,
-
- input wire [31 : 0] H6_wr_data,
- input wire H6_we,
-
- input wire [31 : 0] H7_wr_data,
- input wire H7_we,
+ input wire [31 : 0] state_wr_data,
+ input wire state0_we,
+ input wire state1_we,
+ input wire state2_we,
+ input wire state3_we,
+ input wire state4_we,
+ input wire state5_we,
+ input wire state6_we,
+ input wire state7_we,
output wire ready,
@@ -262,6 +248,30 @@ module sha256_core(
H7_reg <= H7_new;
end
+ if (state0_we)
+ H0_reg <= state_wr_data;
+
+ if (state1_we)
+ H1_reg <= state_wr_data;
+
+ if (state2_we)
+ H2_reg <= state_wr_data;
+
+ if (state3_we)
+ H3_reg <= state_wr_data;
+
+ if (state4_we)
+ H4_reg <= state_wr_data;
+
+ if (state5_we)
+ H5_reg <= state_wr_data;
+
+ if (state6_we)
+ H6_reg <= state_wr_data;
+
+ if (state7_we)
+ H7_reg <= state_wr_data;
+
if (t_ctr_we)
begin
t_ctr_reg <= t_ctr_new;