The digest is the complete state so we only need to be able to write back state. The state addresses are still readable though.

2 files changed, 9 insertions, 32 deletions

diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index 551e3b9..7f1dc94 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -171,21 +171,13 @@ module sha256(
   wire [255 : 0] core_digest;
   wire           core_digest_valid;
 
-  wire [31 : 0]  state0_rd_data;
   reg            state0_we;
-  wire [31 : 0]  state1_rd_data;
   reg            state1_we;
-  wire [31 : 0]  state2_rd_data;
   reg            state2_we;
-  wire [31 : 0]  state3_rd_data;
   reg            state3_we;
-  wire [31 : 0]  state4_rd_data;
   reg            state4_we;
-  wire [31 : 0]  state5_rd_data;
   reg            state5_we;
-  wire [31 : 0]  state6_rd_data;
   reg            state6_we;
-  wire [31 : 0]  state7_rd_data;
   reg            state7_we;
 
   reg [31 : 0]   tmp_read_data;
@@ -223,35 +215,27 @@ module sha256(
                    // State access ports
                    .H0_wr_data(write_data),
                    .H0_we(state0_we),
-                   .H0_rd_data(state0_rd_data),
 
                    .H1_wr_data(write_data),
                    .H1_we(state1_we),
-                   .H1_rd_data(state1_rd_data),
 
                    .H2_wr_data(write_data),
                    .H2_we(state2_we),
-                   .H2_rd_data(state2_rd_data),
 
                    .H3_wr_data(write_data),
                    .H3_we(state3_we),
-                   .H3_rd_data(state3_rd_data),
 
                    .H4_wr_data(write_data),
                    .H4_we(state4_we),
-                   .H4_rd_data(state4_rd_data),
 
                    .H5_wr_data(write_data),
                    .H5_we(state5_we),
-                   .H5_rd_data(state5_rd_data),
 
                    .H6_wr_data(write_data),
                    .H6_we(state6_we),
-                   .H6_rd_data(state6_rd_data),
 
                    .H7_wr_data(write_data),
                    .H7_we(state7_we),
-                   .H7_rd_data(state7_rd_data),
 
                    .ready(core_ready),
 
@@ -743,29 +727,30 @@ module sha256(
                     tmp_read_data = digest_reg[31  :   0];
                   end
 
+
                 ADDR_STATE0:
-                  tmp_read_data = state0_rd_data;
+                  tmp_read_data = digest_reg[255 : 224];
 
                 ADDR_STATE1:
-                  tmp_read_data = state1_rd_data;
+                  tmp_read_data = digest_reg[223 : 192];
 
                 ADDR_STATE2:
-                  tmp_read_data = state2_rd_data;
+                  tmp_read_data = digest_reg[191 : 160];
 
                 ADDR_STATE3:
-                  tmp_read_data = state3_rd_data;
+                  tmp_read_data = digest_reg[159 : 128];
 
                 ADDR_STATE4:
-                  tmp_read_data = state4_rd_data;
+                  tmp_read_data = digest_reg[127 :  96];
 
                 ADDR_STATE5:
-                  tmp_read_data = state5_rd_data;
+                  tmp_read_data = digest_reg[95  :  64];
 
                 ADDR_STATE6:
-                  tmp_read_data = state6_rd_data;
+                  tmp_read_data = digest_reg[63  :  32];
 
                 ADDR_STATE7:
-                  tmp_read_data = state7_rd_data;
+                  tmp_read_data = digest_reg[31  :   0];
 
                 default:
                   begin
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index dbcec3b..fa21862 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -48,35 +48,27 @@ module sha256_core(
                    // State access ports
                    input wire [31 : 0]   H0_wr_data,
                    input wire            H0_we,
-                   output wire [31 : 0]  H0_rd_data,
 
                    input wire [31 : 0]   H1_wr_data,
                    input wire            H1_we,
-                   output wire [31 : 0]  H1_rd_data,
 
                    input wire [31 : 0]   H2_wr_data,
                    input wire            H2_we,
-                   output wire [31 : 0]  H2_rd_data,
 
                    input wire [31 : 0]   H3_wr_data,
                    input wire            H3_we,
-                   output wire [31 : 0]  H3_rd_data,
 
                    input wire [31 : 0]   H4_wr_data,
                    input wire            H4_we,
-                   output wire [31 : 0]  H4_rd_data,
 
                    input wire [31 : 0]   H5_wr_data,
                    input wire            H5_we,
-                   output wire [31 : 0]  H5_rd_data,
 
                    input wire [31 : 0]   H6_wr_data,
                    input wire            H6_we,
-                   output wire [31 : 0]  H6_rd_data,
 
                    input wire [31 : 0]   H7_wr_data,
                    input wire            H7_we,
-                   output wire [31 : 0]  H7_rd_data,
 
                    output wire           ready,