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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-11-06 13:18:57 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-11-06 13:18:57 +0100
commitc4cd88c7b8375b4696a6533ed419ddee3156ba9b (patch)
treee5ce99837d466f09ac4913162d14a70f5b6deca6 /src/rtl
parent3c7c7c3b829c857e72d75d5054e39f6e0417c58f (diff)
Fixed nits found using verilator linter. Removed trailing whitespace.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha256_core.v157
1 files changed, 77 insertions, 80 deletions
diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index 5035954..d4330d9 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -8,30 +8,30 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014 SUNET
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -39,19 +39,19 @@
module sha256_core(
input wire clk,
input wire reset_n,
-
+
input wire init,
input wire next,
input wire [511 : 0] block,
-
+
output wire ready,
-
+
output wire [255 : 0] digest,
output wire digest_valid
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -65,12 +65,12 @@ module sha256_core(
parameter H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
-
+
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -109,7 +109,7 @@ module sha256_core(
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
-
+
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
@@ -119,12 +119,12 @@ module sha256_core(
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
-
+
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
-
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
@@ -146,40 +146,40 @@ module sha256_core(
reg w_init;
reg w_next;
wire [31 : 0] w_data;
-
-
+
+
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
- sha256_k_constants k_constants(
- .addr(t_ctr_reg),
- .K(k_data)
- );
+ sha256_k_constants k_constants_inst(
+ .addr(t_ctr_reg),
+ .K(k_data)
+ );
+
+ sha256_w_mem w_mem_inst(
+ .clk(clk),
+ .reset_n(reset_n),
- sha256_w_mem w_mem(
- .clk(clk),
- .reset_n(reset_n),
+ .block(block),
- .block(block),
+ .init(w_init),
+ .next(w_next),
+ .w(w_data)
+ );
- .init(w_init),
- .next(w_next),
- .w(w_data)
- );
-
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
-
+
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
-
+
assign digest_valid = digest_valid_reg;
-
-
+
+
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
@@ -212,7 +212,7 @@ module sha256_core(
end
else
begin
-
+
if (a_h_we)
begin
a_reg <= a_new;
@@ -236,7 +236,7 @@ module sha256_core(
H6_reg <= H6_new;
H7_reg <= H7_new;
end
-
+
if (t_ctr_we)
begin
t_ctr_reg <= t_ctr_new;
@@ -246,7 +246,7 @@ module sha256_core(
begin
digest_valid_reg <= digest_valid_new;
end
-
+
if (sha256_ctrl_we)
begin
sha256_ctrl_reg <= sha256_ctrl_new;
@@ -254,7 +254,7 @@ module sha256_core(
end
end // reg_update
-
+
//----------------------------------------------------------------
// digest_logic
//
@@ -310,12 +310,12 @@ module sha256_core(
reg [31 : 0] sum1;
reg [31 : 0] ch;
- sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
- {e_reg[10 : 0], e_reg[31 : 11]} ^
+ sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
+ {e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
-
+
t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
@@ -335,11 +335,11 @@ module sha256_core(
{a_reg[21 : 0], a_reg[31 : 22]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
-
+
t2 = sum0 + maj;
end // t2_logic
-
-
+
+
//----------------------------------------------------------------
// state_logic
//
@@ -348,9 +348,6 @@ module sha256_core(
//----------------------------------------------------------------
always @*
begin : state_logic
- reg [31 : 0] tmp1;
- reg [31 : 0] tmp2;
-
a_new = 32'h00000000;
b_new = 32'h00000000;
c_new = 32'h00000000;
@@ -360,7 +357,7 @@ module sha256_core(
g_new = 32'h00000000;
h_new = 32'h00000000;
a_h_we = 0;
-
+
if (state_init)
begin
if (first_block)
@@ -388,7 +385,7 @@ module sha256_core(
a_h_we = 1;
end
end
-
+
if (state_update)
begin
a_new = t1 + t2;
@@ -403,18 +400,18 @@ module sha256_core(
end
end // state_logic
-
+
//----------------------------------------------------------------
// t_ctr
//
- // Update logic for the round counter, a monotonically
+ // Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
-
+
if (t_ctr_rst)
begin
t_ctr_new = 0;
@@ -428,7 +425,7 @@ module sha256_core(
end
end // t_ctr
-
+
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
@@ -441,28 +438,28 @@ module sha256_core(
state_init = 0;
state_update = 0;
-
+
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
-
+
t_ctr_inc = 0;
t_ctr_rst = 0;
-
+
digest_valid_new = 0;
digest_valid_we = 0;
-
+
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
-
+
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
-
+
if (init)
begin
digest_init = 1;
@@ -488,7 +485,7 @@ module sha256_core(
end
end
-
+
CTRL_ROUNDS:
begin
w_next = 1;
@@ -502,7 +499,7 @@ module sha256_core(
end
end
-
+
CTRL_DONE:
begin
digest_update = 1;
@@ -514,7 +511,7 @@ module sha256_core(
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
-
+
endmodule // sha256_core
//======================================================================