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-rw-r--r--src/rtl/sha256_w_mem.v113
-rw-r--r--src/tb/tb_sha256.v52
-rw-r--r--src/tb/tb_sha256_core.v42
-rw-r--r--src/tb/tb_sha256_w_mem.v101
4 files changed, 105 insertions, 203 deletions
diff --git a/src/rtl/sha256_w_mem.v b/src/rtl/sha256_w_mem.v
index 501cef0..fef1205 100644
--- a/src/rtl/sha256_w_mem.v
+++ b/src/rtl/sha256_w_mem.v
@@ -51,13 +51,6 @@ module sha256_w_mem(
//----------------------------------------------------------------
- // Internal constant and parameter definitions.
- //----------------------------------------------------------------
- parameter CTRL_IDLE = 0;
- parameter CTRL_UPDATE = 1;
-
-
- //----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
@@ -82,12 +75,6 @@ module sha256_w_mem(
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
- reg w_ctr_inc;
- reg w_ctr_rst;
-
- reg [1 : 0] sha256_w_mem_ctrl_reg;
- reg [1 : 0] sha256_w_mem_ctrl_new;
- reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
@@ -111,26 +98,14 @@ module sha256_w_mem(
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
+ integer i;
+
if (!reset_n)
begin
- w_mem[00] <= 32'h00000000;
- w_mem[01] <= 32'h00000000;
- w_mem[02] <= 32'h00000000;
- w_mem[03] <= 32'h00000000;
- w_mem[04] <= 32'h00000000;
- w_mem[05] <= 32'h00000000;
- w_mem[06] <= 32'h00000000;
- w_mem[07] <= 32'h00000000;
- w_mem[08] <= 32'h00000000;
- w_mem[09] <= 32'h00000000;
- w_mem[10] <= 32'h00000000;
- w_mem[11] <= 32'h00000000;
- w_mem[12] <= 32'h00000000;
- w_mem[13] <= 32'h00000000;
- w_mem[14] <= 32'h00000000;
- w_mem[15] <= 32'h00000000;
- w_ctr_reg <= 6'h00;
- sha256_w_mem_ctrl_reg <= CTRL_IDLE;
+ for (i = 0 ; i < 16 ; i = i + 1)
+ w_mem[i] <= 32'h0;
+
+ w_ctr_reg <= 6'h0;
end
else
begin
@@ -155,14 +130,7 @@ module sha256_w_mem(
end
if (w_ctr_we)
- begin
- w_ctr_reg <= w_ctr_new;
- end
-
- if (sha256_w_mem_ctrl_we)
- begin
- sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
- end
+ w_ctr_reg <= w_ctr_new;
end
end // reg_update
@@ -176,13 +144,9 @@ module sha256_w_mem(
always @*
begin : select_w
if (w_ctr_reg < 16)
- begin
- w_tmp = w_mem[w_ctr_reg[3 : 0]];
- end
+ w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
- begin
- w_tmp = w_new;
- end
+ w_tmp = w_new;
end // select_w
@@ -254,7 +218,8 @@ module sha256_w_mem(
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
- else if (w_ctr_reg > 15)
+
+ if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
@@ -284,62 +249,22 @@ module sha256_w_mem(
//----------------------------------------------------------------
always @*
begin : w_ctr
- w_ctr_new = 0;
- w_ctr_we = 0;
+ w_ctr_new = 6'h0;
+ w_ctr_we = 1'h0;
- if (w_ctr_rst)
+ if (init)
begin
- w_ctr_new = 6'h00;
- w_ctr_we = 1;
+ w_ctr_new = 6'h0;
+ w_ctr_we = 1'h1;
end
- if (w_ctr_inc)
+ if (next)
begin
- w_ctr_new = w_ctr_reg + 6'h01;
- w_ctr_we = 1;
+ w_ctr_new = w_ctr_reg + 6'h1;
+ w_ctr_we = 1'h1;
end
end // w_ctr
-
- //----------------------------------------------------------------
- // sha256_w_mem_fsm
- // Logic for the w shedule FSM.
- //----------------------------------------------------------------
- always @*
- begin : sha256_w_mem_fsm
- w_ctr_rst = 0;
- w_ctr_inc = 0;
-
- sha256_w_mem_ctrl_new = CTRL_IDLE;
- sha256_w_mem_ctrl_we = 0;
-
- case (sha256_w_mem_ctrl_reg)
- CTRL_IDLE:
- begin
- if (init)
- begin
- w_ctr_rst = 1;
- sha256_w_mem_ctrl_new = CTRL_UPDATE;
- sha256_w_mem_ctrl_we = 1;
- end
- end
-
- CTRL_UPDATE:
- begin
- if (next)
- begin
- w_ctr_inc = 1;
- end
-
- if (w_ctr_reg == 6'h3f)
- begin
- sha256_w_mem_ctrl_new = CTRL_IDLE;
- sha256_w_mem_ctrl_we = 1;
- end
- end
- endcase // case (sha256_ctrl_reg)
- end // sha256_ctrl_fsm
-
endmodule // sha256_w_mem
//======================================================================
diff --git a/src/tb/tb_sha256.v b/src/tb/tb_sha256.v
index 6377688..01aa66e 100644
--- a/src/tb/tb_sha256.v
+++ b/src/tb/tb_sha256.v
@@ -38,12 +38,6 @@
//======================================================================
//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
-
-//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_sha256();
@@ -167,7 +161,7 @@ module tb_sha256();
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
@@ -211,7 +205,7 @@ module tb_sha256();
//
// Dump the state of the H registers when needed.
//----------------------------------------------------------------
- task dump_H_state();
+ task dump_H_state;
begin
$display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg);
@@ -227,7 +221,7 @@ module tb_sha256();
//
// Toggles reset to force the DUT into a well defined state.
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -243,7 +237,7 @@ module tb_sha256();
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
cycle_ctr = 32'h00000000;
error_ctr = 32'h00000000;
@@ -264,7 +258,7 @@ module tb_sha256();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_result();
+ task display_test_result;
begin
if (error_ctr == 0)
begin
@@ -289,7 +283,7 @@ module tb_sha256();
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
- task wait_ready();
+ task wait_ready;
begin
read_data = 0;
@@ -383,7 +377,7 @@ module tb_sha256();
//
// Read the name and version from the DUT.
//----------------------------------------------------------------
- task check_name_version();
+ task check_name_version;
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
@@ -411,7 +405,7 @@ module tb_sha256();
// Read the digest in the dut. The resulting digest will be
// available in the global variable digest_data.
//----------------------------------------------------------------
- task read_digest();
+ task read_digest;
begin
read_word(ADDR_DIGEST0);
digest_data[255 : 224] = read_data;
@@ -453,8 +447,8 @@ module tb_sha256();
write_word(ADDR_CTRL, CTRL_INIT_VALUE);
#(CLK_PERIOD);
- wait_ready();
- read_digest();
+ wait_ready;
+ read_digest;
// We need to ignore the LSW in SHA224 mode.
if (mode == SHA224_MODE)
@@ -502,8 +496,8 @@ module tb_sha256();
write_word(ADDR_CTRL, CTRL_INIT_VALUE);
#(CLK_PERIOD);
- wait_ready();
- read_digest();
+ wait_ready;
+ read_digest;
// We need to ignore the LSW in SHA224 mode.
if (mode == SHA224_MODE)
@@ -530,8 +524,8 @@ module tb_sha256();
write_word(ADDR_CTRL, CTRL_NEXT_VALUE);
#(CLK_PERIOD);
- wait_ready();
- read_digest();
+ wait_ready;
+ read_digest;
// We need to ignore the LSW in SHA224 mode.
if (mode == SHA224_MODE)
@@ -587,8 +581,8 @@ module tb_sha256();
write_block(block);
write_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
#(CLK_PERIOD);
- wait_ready();
- read_digest();
+ wait_ready;
+ read_digest;
if (digest_data == expected)
begin
@@ -685,15 +679,15 @@ module tb_sha256();
begin : sha256_top_test
$display(" -- Testbench for sha256 started --");
- init_sim();
- reset_dut();
+ init_sim;
+ reset_dut;
- check_name_version();
- sha224_tests();
- sha256_tests();
- restore_state_test();
+ check_name_version;
+ sha224_tests;
+ sha256_tests;
+ restore_state_test;
- display_test_result();
+ display_test_result;
$display(" -- Testbench for sha256 done. --");
$finish;
diff --git a/src/tb/tb_sha256_core.v b/src/tb/tb_sha256_core.v
index 981351c..3b76aca 100644
--- a/src/tb/tb_sha256_core.v
+++ b/src/tb/tb_sha256_core.v
@@ -38,12 +38,6 @@
//======================================================================
//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
-
-//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_sha256_core();
@@ -138,7 +132,7 @@ module tb_sha256_core();
#(2 * CLK_HALF_PERIOD);
if (DEBUG)
begin
- dump_dut_state();
+ dump_dut_state;
end
end
@@ -148,7 +142,7 @@ module tb_sha256_core();
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
@@ -203,7 +197,7 @@ module tb_sha256_core();
//
// Dump the state of the H registers when needed.
//----------------------------------------------------------------
- task dump_H_state();
+ task dump_H_state;
begin
$display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
@@ -219,7 +213,7 @@ module tb_sha256_core();
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -235,7 +229,7 @@ module tb_sha256_core();
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
@@ -266,7 +260,7 @@ module tb_sha256_core();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_result();
+ task display_test_result;
begin
if (error_ctr == 0)
begin
@@ -289,7 +283,7 @@ module tb_sha256_core();
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
- task wait_ready();
+ task wait_ready;
begin
while (!tb_ready)
begin
@@ -308,7 +302,7 @@ module tb_sha256_core();
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
- task wait_data_valid();
+ task wait_data_valid;
begin
while (!tb_digest_valid)
begin
@@ -334,7 +328,7 @@ module tb_sha256_core();
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
- wait_ready();
+ wait_ready;
if (tb_digest == expected)
begin
@@ -378,18 +372,18 @@ module tb_sha256_core();
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
- wait_ready();
+ wait_ready;
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
- dump_dut_state();
+ dump_dut_state;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
- wait_ready();
+ wait_ready;
$display("*** TC %0d second block done.", tc_number);
@@ -496,7 +490,7 @@ module tb_sha256_core();
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
- wait_ready();
+ wait_ready;
$display("*** TC %0d block done.", tc_number);
if (tb_digest == expected)
@@ -544,10 +538,10 @@ module tb_sha256_core();
$display(" -- Testbench for sha256 core started --");
- init_sim();
- dump_dut_state();
- reset_dut();
- dump_dut_state();
+ init_sim;
+ dump_dut_state;
+ reset_dut;
+ dump_dut_state;
// TC1: Single block message: "abc".
tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
@@ -568,7 +562,7 @@ module tb_sha256_core();
tc3_res = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
state_restore_test(3, tc3_state, tc3_block, tc3_res);
- display_test_result();
+ display_test_result;
$display("*** Simulation done.");
$finish;
end // sha256_core_test
diff --git a/src/tb/tb_sha256_w_mem.v b/src/tb/tb_sha256_w_mem.v
index 9fdf063..c318a4d 100644
--- a/src/tb/tb_sha256_w_mem.v
+++ b/src/tb/tb_sha256_w_mem.v
@@ -8,7 +8,7 @@
// Author: Joachim Strombergson
// Copyright (c) 2014 NORDUnet A/S
// All rights reserved.
-//
+//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
@@ -37,11 +37,6 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
module tb_sha256_w_mem();
//----------------------------------------------------------------
@@ -52,55 +47,50 @@ module tb_sha256_w_mem();
parameter CLK_HALF_PERIOD = 2;
-
- //----------------------------------------------------------------
- // Registers including update variables and write enable.
- //----------------------------------------------------------------
-
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg tb_clk;
- reg tb_reset_n;
+ reg tb_clk;
+ reg tb_reset_n;
reg tb_init;
reg tb_next;
reg [511 : 0] tb_block;
wire [31 : 0] tb_w;
- reg [63 : 0] cycle_ctr;
- reg [31 : 0] error_ctr;
- reg [31 : 0] tc_ctr;
-
-
+ reg [63 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha256_w_mem dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
-
+
.block(tb_block),
-
+
.init(tb_init),
.next(tb_next),
.w(tb_w)
);
-
+
//----------------------------------------------------------------
// clk_gen
//
- // Clock generator process.
+ // Clock generator process.
//----------------------------------------------------------------
- always
+ always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
-
+
//--------------------------------------------------------------------
// dut_monitor
//
@@ -115,48 +105,47 @@ module tb_sha256_w_mem();
begin
$display("cycle = %016x:", cycle_ctr);
end
-
+
if (DEBUG)
begin
- $display("dut ctrl_state = %02x:", dut.sha256_w_mem_ctrl_reg);
- $display("dut w_ctr = %02x:", dut.w_ctr_reg);
- $display("dut w_tmp = %02x:", dut.w_tmp);
- dump_w_state();
+ $display("dut w_ctr = %02x:", dut.w_ctr_reg);
+ $display("dut w_tmp = %02x:", dut.w_tmp);
+ dump_w_state;
end
end // dut_monitor
-
-
+
+
//----------------------------------------------------------------
// dump_w_state()
//
// Dump the current state of all W registers.
//----------------------------------------------------------------
- task dump_w_state();
+ task dump_w_state;
begin
$display("W state:");
-
- $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x",
+
+ $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x",
dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);
- $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x",
+ $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x",
dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);
- $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x",
+ $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x",
dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);
- $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
+ $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);
$display("w_new = %08x", dut.w_new);
$display("");
end
endtask // dump_state
-
-
+
+
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -164,61 +153,61 @@ module tb_sha256_w_mem();
tb_reset_n = 1;
end
endtask // reset_dut
-
-
+
+
//----------------------------------------------------------------
// init_sim
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
$display("*** Simulation init.");
tb_clk = 0;
tb_reset_n = 1;
cycle_ctr = 0;
-
+
tb_init = 0;
tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
end
endtask // reset_dut
-
-
+
+
//----------------------------------------------------------------
// test_w_schedule()
//
// Test that W scheduling happens and work correctly.
// Note: Currently not a self checking test case.
//----------------------------------------------------------------
- task test_w_schedule();
+ task test_w_schedule;
begin
$display("*** Test of W schedule processing. --");
tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
tb_init = 1;
#(4 * CLK_HALF_PERIOD);
tb_init = 0;
- dump_w_state();
+ dump_w_state;
tb_next = 1;
#(150 * CLK_HALF_PERIOD);
end
endtask // test_w_schedule
-
-
+
+
//----------------------------------------------------------------
- // The main test functionality.
+ // The main test functionality.
//----------------------------------------------------------------
initial
begin : w_mem_test
$display(" -- Testbench for sha256 w memory started --");
- init_sim();
- reset_dut();
- test_w_schedule();
+ init_sim;
+ reset_dut;
+ test_w_schedule;
$display("*** Simulation done.");
$finish;
end
-
+
endmodule // w_mem_test
-
+
//======================================================================
// EOF tb_sha256_w_mem.v
//======================================================================
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 20:52:09 +0000