diff options
Diffstat (limited to 'src/tb/tb_sha256_w_mem.v')
| -rw-r--r-- | src/tb/tb_sha256_w_mem.v | 101 |
1 files changed, 45 insertions, 56 deletions
diff --git a/src/tb/tb_sha256_w_mem.v b/src/tb/tb_sha256_w_mem.v index 9fdf063..c318a4d 100644 --- a/src/tb/tb_sha256_w_mem.v +++ b/src/tb/tb_sha256_w_mem.v @@ -8,7 +8,7 @@ // Author: Joachim Strombergson // Copyright (c) 2014 NORDUnet A/S // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -37,11 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - module tb_sha256_w_mem(); //---------------------------------------------------------------- @@ -52,55 +47,50 @@ module tb_sha256_w_mem(); parameter CLK_HALF_PERIOD = 2; - - //---------------------------------------------------------------- - // Registers including update variables and write enable. - //---------------------------------------------------------------- - //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg tb_clk; - reg tb_reset_n; + reg tb_clk; + reg tb_reset_n; reg tb_init; reg tb_next; reg [511 : 0] tb_block; wire [31 : 0] tb_w; - reg [63 : 0] cycle_ctr; - reg [31 : 0] error_ctr; - reg [31 : 0] tc_ctr; - - + reg [63 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha256_w_mem dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .block(tb_block), - + .init(tb_init), .next(tb_next), .w(tb_w) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //-------------------------------------------------------------------- // dut_monitor // @@ -115,48 +105,47 @@ module tb_sha256_w_mem(); begin $display("cycle = %016x:", cycle_ctr); end - + if (DEBUG) begin - $display("dut ctrl_state = %02x:", dut.sha256_w_mem_ctrl_reg); - $display("dut w_ctr = %02x:", dut.w_ctr_reg); - $display("dut w_tmp = %02x:", dut.w_tmp); - dump_w_state(); + $display("dut w_ctr = %02x:", dut.w_ctr_reg); + $display("dut w_tmp = %02x:", dut.w_tmp); + dump_w_state; end end // dut_monitor - - + + //---------------------------------------------------------------- // dump_w_state() // // Dump the current state of all W registers. //---------------------------------------------------------------- - task dump_w_state(); + task dump_w_state; begin $display("W state:"); - - $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x", + + $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x", dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]); - $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x", + $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x", dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]); - $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x", + $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x", dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]); - $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", + $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]); $display("w_new = %08x", dut.w_new); $display(""); end endtask // dump_state - - + + //---------------------------------------------------------------- // reset_dut //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -164,61 +153,61 @@ module tb_sha256_w_mem(); tb_reset_n = 1; end endtask // reset_dut - - + + //---------------------------------------------------------------- // init_sim //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin $display("*** Simulation init."); tb_clk = 0; tb_reset_n = 1; cycle_ctr = 0; - + tb_init = 0; tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; end endtask // reset_dut - - + + //---------------------------------------------------------------- // test_w_schedule() // // Test that W scheduling happens and work correctly. // Note: Currently not a self checking test case. //---------------------------------------------------------------- - task test_w_schedule(); + task test_w_schedule; begin $display("*** Test of W schedule processing. --"); tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; tb_init = 1; #(4 * CLK_HALF_PERIOD); tb_init = 0; - dump_w_state(); + dump_w_state; tb_next = 1; #(150 * CLK_HALF_PERIOD); end endtask // test_w_schedule - - + + //---------------------------------------------------------------- - // The main test functionality. + // The main test functionality. //---------------------------------------------------------------- initial begin : w_mem_test $display(" -- Testbench for sha256 w memory started --"); - init_sim(); - reset_dut(); - test_w_schedule(); + init_sim; + reset_dut; + test_w_schedule; $display("*** Simulation done."); $finish; end - + endmodule // w_mem_test - + //====================================================================== // EOF tb_sha256_w_mem.v //====================================================================== |