1 files changed, 18 insertions, 24 deletions

diff --git a/src/tb/tb_sha256_core.v b/src/tb/tb_sha256_core.v
index 981351c..3b76aca 100644
--- a/src/tb/tb_sha256_core.v
+++ b/src/tb/tb_sha256_core.v
@@ -38,12 +38,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_sha256_core();
@@ -138,7 +132,7 @@ module tb_sha256_core();
       #(2 * CLK_HALF_PERIOD);
       if (DEBUG)
         begin
-          dump_dut_state();
+          dump_dut_state;
         end
     end
 
@@ -148,7 +142,7 @@ module tb_sha256_core();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -203,7 +197,7 @@ module tb_sha256_core();
   //
   // Dump the state of the H registers when needed.
   //----------------------------------------------------------------
-  task dump_H_state();
+  task dump_H_state;
     begin
       $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
                dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
@@ -219,7 +213,7 @@ module tb_sha256_core();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -235,7 +229,7 @@ module tb_sha256_core();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr        = 0;
       error_ctr        = 0;
@@ -266,7 +260,7 @@ module tb_sha256_core();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
@@ -289,7 +283,7 @@ module tb_sha256_core();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       while (!tb_ready)
         begin
@@ -308,7 +302,7 @@ module tb_sha256_core();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_data_valid();
+  task wait_data_valid;
     begin
       while (!tb_digest_valid)
         begin
@@ -334,7 +328,7 @@ module tb_sha256_core();
      tb_init = 1;
      #(CLK_PERIOD);
      tb_init = 0;
-     wait_ready();
+     wait_ready;
 
      if (tb_digest == expected)
        begin
@@ -378,18 +372,18 @@ module tb_sha256_core();
      tb_init = 1;
      #(CLK_PERIOD);
      tb_init = 0;
-     wait_ready();
+     wait_ready;
 
      db_digest1 = tb_digest;
      $display("*** TC %0d first block done.", tc_number);
 
      $display("*** TC %0d second block started.", tc_number);
      tb_block = block2;
-     dump_dut_state();
+     dump_dut_state;
      tb_next = 1;
      #(CLK_PERIOD);
      tb_next = 0;
-     wait_ready();
+     wait_ready;
 
      $display("*** TC %0d second block done.", tc_number);
 
@@ -496,7 +490,7 @@ module tb_sha256_core();
      tb_next = 1;
      #(CLK_PERIOD);
      tb_next = 0;
-     wait_ready();
+     wait_ready;
      $display("*** TC %0d block done.", tc_number);
 
      if (tb_digest == expected)
@@ -544,10 +538,10 @@ module tb_sha256_core();
 
       $display("   -- Testbench for sha256 core started --");
 
-      init_sim();
-      dump_dut_state();
-      reset_dut();
-      dump_dut_state();
+      init_sim;
+      dump_dut_state;
+      reset_dut;
+      dump_dut_state;
 
       // TC1: Single block message: "abc".
       tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
@@ -568,7 +562,7 @@ module tb_sha256_core();
       tc3_res = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
       state_restore_test(3, tc3_state, tc3_block, tc3_res);
 
-      display_test_result();
+      display_test_result;
       $display("*** Simulation done.");
       $finish;
     end // sha256_core_test