| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-05-12 | Adding the functionality to extractd and set the intrnal hash state. Note: Th...HEADmaster | Joachim Strömbergson |
| 2020-05-12 | Minor change. variable names are easier to read. | Joachim Strömbergson |
| 2018-04-27 | Removed redundant FSM from the W memory. | Joachim Strömbergson |
| 2017-12-08 | Syncecd SHA-1 core to github repo. No functional changes, but more compact co... | Joachim Strömbergson |
| 2015-12-13 | whack copyrights | Paul Selkirk |
| 2014-11-06 | (1) Minor fixes of nits found by the verilator linter. (2) Removed trailing w... | Joachim Strömbergson |
| 2014-03-16 | Added wait to allow the ready flag to be dropped with resettable flags. Fixed... | Joachim Strömbergson |
| 2014-03-14 | Updating interface. Addding self resetting control regs. Fixing missing input... | Joachim Strömbergson |
| 2014-02-23 | Updated W memory module with new sliding window version. Updated README with ... | Joachim Strömbergson |
| 2014-02-21 | Adding all testbenches. | Joachim Strömbergson |
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index : core/hash/sha1 | |
| Verilog implementation of the SHA-1 cryptographic hash function | git repositories |
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