(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing whitespace.

1 files changed, 61 insertions, 62 deletions

diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v
index 9ad16da..7426bcd 100644
--- a/src/tb/tb_sha1_w_mem.v
+++ b/src/tb/tb_sha1_w_mem.v
@@ -7,30 +7,30 @@
 //
 // Author: Joachim Strombergson
 // Copyright (c) 2014 SUNET
-// 
-// Redistribution and use in source and binary forms, with or 
-// without modification, are permitted provided that the following 
-// conditions are met: 
-// 
-// 1. Redistributions of source code must retain the above copyright 
-//    notice, this list of conditions and the following disclaimer. 
-// 
-// 2. Redistributions in binary form must reproduce the above copyright 
-//    notice, this list of conditions and the following disclaimer in 
-//    the documentation and/or other materials provided with the 
-//    distribution. 
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 //======================================================================
@@ -42,7 +42,7 @@
 
 module tb_sha1_w_mem();
 
-  
+
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
@@ -51,12 +51,12 @@ module tb_sha1_w_mem();
 
   parameter CLK_HALF_PERIOD = 2;
 
-  
+
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
 
-  
+
   //----------------------------------------------------------------
   // Wires.
   //----------------------------------------------------------------
@@ -70,35 +70,35 @@ module tb_sha1_w_mem();
   reg [63 : 0] cycle_ctr;
   reg [31 : 0] error_ctr;
   reg [31 : 0] tc_ctr;
-  
-  
+
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
   sha1_w_mem dut(
                  .clk(tb_clk),
                  .reset_n(tb_reset_n),
-                 
+
                  .block(tb_block),
 
                  .init(tb_init),
                  .next(tb_next),
-                 
+
                  .w(tb_w)
                 );
-  
+
 
   //----------------------------------------------------------------
   // clk_gen
   //
-  // Clock generator process. 
+  // Clock generator process.
   //----------------------------------------------------------------
-  always 
+  always
     begin : clk_gen
       #CLK_HALF_PERIOD tb_clk = !tb_clk;
     end // clk_gen
 
-  
+
   //--------------------------------------------------------------------
   // dut_monitor
   //
@@ -119,8 +119,8 @@ module tb_sha1_w_mem();
           dump_w_state();
         end
     end // dut_monitor
-      
-  
+
+
   //----------------------------------------------------------------
   // dump_w_state()
   //
@@ -130,30 +130,29 @@ module tb_sha1_w_mem();
     begin
       $display("W state:");
 
-      
-      $display("ctrl_reg = %01x, w_ctr_reg = %02x, mem_update = %01x, init = %01x, next = %01x", 
-               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.mem_update, 
-               dut.init, dut.next);
-      
+
+      $display("ctrl_reg = %01x, w_ctr_reg = %02x, init = %01x, next = %01x",
+               dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);
+
       $display("w_tmp   = %08x, w_new   = %08x", dut.w_tmp, dut.w_new);
- 
-      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x", 
+
+      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x",
                dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);
 
-      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x", 
+      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x",
                dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);
 
-      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x", 
+      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x",
                dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);
 
-      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", 
+      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
                dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);
 
       $display("");
     end
   endtask // dump_state
-  
-  
+
+
   //----------------------------------------------------------------
   // reset_dut
   //----------------------------------------------------------------
@@ -165,8 +164,8 @@ module tb_sha1_w_mem();
       tb_reset_n = 1;
     end
   endtask // reset_dut
-  
-  
+
+
   //----------------------------------------------------------------
   // init_sim
   //----------------------------------------------------------------
@@ -182,7 +181,7 @@ module tb_sha1_w_mem();
     end
   endtask // reset_dut
 
-  
+
   //----------------------------------------------------------------
   // dump_mem()
   //
@@ -211,8 +210,8 @@ module tb_sha1_w_mem();
       $display("");
     end
   endtask // dump_mem
-  
-  
+
+
   //----------------------------------------------------------------
   // test_w_schedule()
   //
@@ -229,11 +228,11 @@ module tb_sha1_w_mem();
 
       tb_next = 1;
       #(200 * CLK_HALF_PERIOD);
-      
+
       dump_w_state();
     end
   endtask // test_w_schedule
-  
+
 
   //----------------------------------------------------------------
   // test_read_w/(
@@ -249,7 +248,7 @@ module tb_sha1_w_mem();
       tb_init = 1;
       #(2 * CLK_HALF_PERIOD);
       tb_init = 0;
-      
+
       while (i < 80)
         begin
           tb_next = i;
@@ -259,10 +258,10 @@ module tb_sha1_w_mem();
         end
     end
   endtask // read_w
-  
-    
+
+
   //----------------------------------------------------------------
-  // The main test functionality. 
+  // The main test functionality.
   //----------------------------------------------------------------
   initial
     begin : w_mem_test
@@ -272,7 +271,7 @@ module tb_sha1_w_mem();
       dump_mem();
       reset_dut();
       dump_mem();
-      
+
       test_w_schedule();
 
       test_read_w();
@@ -280,9 +279,9 @@ module tb_sha1_w_mem();
       $display("*** Simulation done.");
       $finish;
     end
-  
+
 endmodule // w_mem_test
-  
+
 //======================================================================
 // EOF tb_sha1_w_mem.v
 //======================================================================