diff options
| -rw-r--r-- | src/rtl/sha1_core.v | 131 | ||||
| -rw-r--r-- | src/rtl/sha1_w_mem.v | 101 | ||||
| -rw-r--r-- | src/tb/tb_sha1_w_mem.v | 123 |
3 files changed, 176 insertions, 179 deletions
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v index aae578c..f38d42f 100644 --- a/src/rtl/sha1_core.v +++ b/src/rtl/sha1_core.v @@ -8,30 +8,30 @@ // // Author: Joachim Strombergson // Copyright (c) 2014 SUNET -// -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: -// -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -39,19 +39,19 @@ module sha1_core( input wire clk, input wire reset_n, - + input wire init, input wire next, input wire [511 : 0] block, - + output wire ready, - + output wire [159 : 0] digest, output wire digest_valid ); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -62,12 +62,12 @@ module sha1_core( parameter H0_4 = 32'hc3d2e1f0; parameter SHA1_ROUNDS = 79; - + parameter CTRL_IDLE = 0; parameter CTRL_ROUNDS = 1; parameter CTRL_DONE = 2; - - + + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- @@ -94,7 +94,7 @@ module sha1_core( reg [31 : 0] H4_reg; reg [31 : 0] H4_new; reg H_we; - + reg [6 : 0] round_ctr_reg; reg [6 : 0] round_ctr_new; reg round_ctr_we; @@ -104,12 +104,12 @@ module sha1_core( reg digest_valid_reg; reg digest_valid_new; reg digest_valid_we; - + reg [1 : 0] sha1_ctrl_reg; reg [1 : 0] sha1_ctrl_new; reg sha1_ctrl_we; - + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- @@ -121,34 +121,33 @@ module sha1_core( reg ready_flag; reg w_init; reg w_next; - wire w_ready; wire [31 : 0] w; - - + + //---------------------------------------------------------------- // Module instantiantions. //---------------------------------------------------------------- - sha1_w_mem w_mem( - .clk(clk), - .reset_n(reset_n), + sha1_w_mem w_mem_inst( + .clk(clk), + .reset_n(reset_n), + + .block(block), - .block(block), + .init(w_init), + .next(w_next), + + .w(w) + ); - .init(w_init), - .next(w_next), - - .w(w) - ); - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign ready = ready_flag; assign digest = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg}; assign digest_valid = digest_valid_reg; - - + + //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. @@ -192,7 +191,7 @@ module sha1_core( H3_reg <= H3_new; H4_reg <= H4_new; end - + if (round_ctr_we) begin round_ctr_reg <= round_ctr_new; @@ -202,7 +201,7 @@ module sha1_core( begin digest_valid_reg <= digest_valid_new; end - + if (sha1_ctrl_we) begin sha1_ctrl_reg <= sha1_ctrl_new; @@ -210,7 +209,7 @@ module sha1_core( end end // reg_update - + //---------------------------------------------------------------- // digest_logic // @@ -245,8 +244,8 @@ module sha1_core( H_we = 1; end end // digest_logic - - + + //---------------------------------------------------------------- // state_logic // @@ -270,7 +269,7 @@ module sha1_core( d_new = 32'h00000000; e_new = 32'h00000000; a_e_we = 0; - + if (state_init) begin if (first_block) @@ -292,7 +291,7 @@ module sha1_core( a_e_we = 1; end end - + if (state_update) begin if (round_ctr_reg <= 19) @@ -315,7 +314,7 @@ module sha1_core( k = 32'hca62c1d6; f = b_reg ^ c_reg ^ d_reg; end - + a5 = {a_reg[26 : 0], a_reg[31 : 27]}; t = a5 + e_reg + f + k + w; @@ -328,18 +327,18 @@ module sha1_core( end end // state_logic - + //---------------------------------------------------------------- // round_ctr // - // Update logic for the round counter, a monotonically + // Update logic for the round counter, a monotonically // increasing counter with reset. //---------------------------------------------------------------- always @* begin : round_ctr round_ctr_new = 0; round_ctr_we = 0; - + if (round_ctr_rst) begin round_ctr_new = 0; @@ -353,7 +352,7 @@ module sha1_core( end end // round_ctr - + //---------------------------------------------------------------- // sha1_ctrl_fsm // Logic for the state machine controlling the core behaviour. @@ -374,12 +373,12 @@ module sha1_core( digest_valid_we = 0; sha1_ctrl_new = CTRL_IDLE; sha1_ctrl_we = 0; - + case (sha1_ctrl_reg) CTRL_IDLE: begin ready_flag = 1; - + if (init) begin digest_init = 1; @@ -405,13 +404,13 @@ module sha1_core( end end - + CTRL_ROUNDS: begin state_update = 1; round_ctr_inc = 1; w_next = 1; - + if (round_ctr_reg == SHA1_ROUNDS) begin sha1_ctrl_new = CTRL_DONE; @@ -419,7 +418,7 @@ module sha1_core( end end - + CTRL_DONE: begin digest_update = 1; @@ -430,7 +429,7 @@ module sha1_core( end endcase // case (sha1_ctrl_reg) end // sha1_ctrl_fsm - + endmodule // sha1_core //====================================================================== diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v index 7b30683..c91a535 100644 --- a/src/rtl/sha1_w_mem.v +++ b/src/rtl/sha1_w_mem.v @@ -9,30 +9,30 @@ // // Author: Joachim Strombergson // Copyright (c) 2014 SUNET -// -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: -// -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -49,7 +49,7 @@ module sha1_w_mem( output wire [31 : 0] w ); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -58,7 +58,7 @@ module sha1_w_mem( parameter CTRL_IDLE = 1'b0; parameter CTRL_UPDATE = 1'b1; - + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- @@ -80,32 +80,31 @@ module sha1_w_mem( reg [31 : 0] w_mem14_new; reg [31 : 0] w_mem15_new; reg w_mem_we; - + reg [6 : 0] w_ctr_reg; reg [6 : 0] w_ctr_new; reg w_ctr_we; reg w_ctr_inc; reg w_ctr_rst; - + reg sha1_w_mem_ctrl_reg; reg sha1_w_mem_ctrl_new; reg sha1_w_mem_ctrl_we; - - + + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- reg [31 : 0] w_tmp; reg [31 : 0] w_new; - reg mem_update; - - + + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- assign w = w_tmp; - - + + //---------------------------------------------------------------- // reg_update // @@ -133,7 +132,7 @@ module sha1_w_mem( w_mem[13] <= 32'h00000000; w_mem[14] <= 32'h00000000; w_mem[15] <= 32'h00000000; - w_ctr_reg <= 7'b0000000; + w_ctr_reg <= 7'h00; sha1_w_mem_ctrl_reg <= CTRL_IDLE; end else @@ -157,12 +156,12 @@ module sha1_w_mem( w_mem[14] <= w_mem14_new; w_mem[15] <= w_mem15_new; end - + if (w_ctr_we) begin w_ctr_reg <= w_ctr_new; end - + if (sha1_w_mem_ctrl_we) begin sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new; @@ -171,11 +170,11 @@ module sha1_w_mem( end end // reg_update - + //---------------------------------------------------------------- // select_w // - // W word selection logic. Returns either directly from the + // W word selection logic. Returns either directly from the // memory or the next w value calculated. //---------------------------------------------------------------- always @* @@ -190,7 +189,7 @@ module sha1_w_mem( end end // w_schedule - + //---------------------------------------------------------------- // w_mem_update_logic // @@ -222,14 +221,14 @@ module sha1_w_mem( w_mem14_new = 32'h00000000; w_mem15_new = 32'h00000000; w_mem_we = 0; - + w_0 = w_mem[0]; w_2 = w_mem[2]; w_8 = w_mem[8]; w_13 = w_mem[13]; w_16 = w_13 ^ w_8 ^ w_2 ^ w_0; w_new = {w_16[30 : 0], w_16[31]}; - + if (init) begin w_mem00_new = block[511 : 480]; @@ -273,7 +272,7 @@ module sha1_w_mem( end end // w_mem_update_logic - + //---------------------------------------------------------------- // w_ctr // @@ -282,23 +281,23 @@ module sha1_w_mem( //---------------------------------------------------------------- always @* begin : w_ctr - w_ctr_new = 0; + w_ctr_new = 7'h00; w_ctr_we = 0; - + if (w_ctr_rst) begin - w_ctr_new = 6'h00; + w_ctr_new = 7'h00; w_ctr_we = 1; end if (w_ctr_inc) begin - w_ctr_new = w_ctr_reg + 6'h01; + w_ctr_new = w_ctr_reg + 7'h01; w_ctr_we = 1; end end // w_ctr - + //---------------------------------------------------------------- // sha1_w_mem_fsm // @@ -310,7 +309,7 @@ module sha1_w_mem( w_ctr_inc = 0; sha1_w_mem_ctrl_new = CTRL_IDLE; sha1_w_mem_ctrl_we = 0; - + case (sha1_w_mem_ctrl_reg) CTRL_IDLE: begin @@ -321,14 +320,14 @@ module sha1_w_mem( sha1_w_mem_ctrl_we = 1; end end - + CTRL_UPDATE: begin if (next) begin w_ctr_inc = 1; end - + if (w_ctr_reg == SHA1_ROUNDS) begin sha1_w_mem_ctrl_new = CTRL_IDLE; diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v index 9ad16da..7426bcd 100644 --- a/src/tb/tb_sha1_w_mem.v +++ b/src/tb/tb_sha1_w_mem.v @@ -7,30 +7,30 @@ // // Author: Joachim Strombergson // Copyright (c) 2014 SUNET -// -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: -// -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -42,7 +42,7 @@ module tb_sha1_w_mem(); - + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -51,12 +51,12 @@ module tb_sha1_w_mem(); parameter CLK_HALF_PERIOD = 2; - + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- - + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- @@ -70,35 +70,35 @@ module tb_sha1_w_mem(); reg [63 : 0] cycle_ctr; reg [31 : 0] error_ctr; reg [31 : 0] tc_ctr; - - + + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- sha1_w_mem dut( .clk(tb_clk), .reset_n(tb_reset_n), - + .block(tb_block), .init(tb_init), .next(tb_next), - + .w(tb_w) ); - + //---------------------------------------------------------------- // clk_gen // - // Clock generator process. + // Clock generator process. //---------------------------------------------------------------- - always + always begin : clk_gen #CLK_HALF_PERIOD tb_clk = !tb_clk; end // clk_gen - + //-------------------------------------------------------------------- // dut_monitor // @@ -119,8 +119,8 @@ module tb_sha1_w_mem(); dump_w_state(); end end // dut_monitor - - + + //---------------------------------------------------------------- // dump_w_state() // @@ -130,30 +130,29 @@ module tb_sha1_w_mem(); begin $display("W state:"); - - $display("ctrl_reg = %01x, w_ctr_reg = %02x, mem_update = %01x, init = %01x, next = %01x", - dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.mem_update, - dut.init, dut.next); - + + $display("ctrl_reg = %01x, w_ctr_reg = %02x, init = %01x, next = %01x", + dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next); + $display("w_tmp = %08x, w_new = %08x", dut.w_tmp, dut.w_new); - - $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x", + + $display("w0_reg = %08x, w1_reg = %08x, w2_reg = %08x, w3_reg = %08x", dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]); - $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x", + $display("w4_reg = %08x, w5_reg = %08x, w6_reg = %08x, w7_reg = %08x", dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]); - $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x", + $display("w8_reg = %08x, w9_reg = %08x, w10_reg = %08x, w11_reg = %08x", dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]); - $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", + $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x", dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]); $display(""); end endtask // dump_state - - + + //---------------------------------------------------------------- // reset_dut //---------------------------------------------------------------- @@ -165,8 +164,8 @@ module tb_sha1_w_mem(); tb_reset_n = 1; end endtask // reset_dut - - + + //---------------------------------------------------------------- // init_sim //---------------------------------------------------------------- @@ -182,7 +181,7 @@ module tb_sha1_w_mem(); end endtask // reset_dut - + //---------------------------------------------------------------- // dump_mem() // @@ -211,8 +210,8 @@ module tb_sha1_w_mem(); $display(""); end endtask // dump_mem - - + + //---------------------------------------------------------------- // test_w_schedule() // @@ -229,11 +228,11 @@ module tb_sha1_w_mem(); tb_next = 1; #(200 * CLK_HALF_PERIOD); - + dump_w_state(); end endtask // test_w_schedule - + //---------------------------------------------------------------- // test_read_w/( @@ -249,7 +248,7 @@ module tb_sha1_w_mem(); tb_init = 1; #(2 * CLK_HALF_PERIOD); tb_init = 0; - + while (i < 80) begin tb_next = i; @@ -259,10 +258,10 @@ module tb_sha1_w_mem(); end end endtask // read_w - - + + //---------------------------------------------------------------- - // The main test functionality. + // The main test functionality. //---------------------------------------------------------------- initial begin : w_mem_test @@ -272,7 +271,7 @@ module tb_sha1_w_mem(); dump_mem(); reset_dut(); dump_mem(); - + test_w_schedule(); test_read_w(); @@ -280,9 +279,9 @@ module tb_sha1_w_mem(); $display("*** Simulation done."); $finish; end - + endmodule // w_mem_test - + //====================================================================== // EOF tb_sha1_w_mem.v //====================================================================== |