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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-05-09 13:14:17 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-05-09 13:14:17 +0200 |
| commit | 10fb68d2e111502ecfd86083b3f8143b661d0406 (patch) | |
| tree | 73ffbc311003ce7690da0f0b0beb21a224fa629d | |
| parent | 01c483ae3f75ac6c4f46425581f0900f99f60109 (diff) | |
Adding a note about the new ability to change bit rate as well as number of data- and stop bits.
| -rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -6,4 +6,9 @@ A Universal asynchronous receiver/transmitter (UART) implemented in Verilog. This UART used to be in coretest, but has been moved out as a separate project. +The current implementation supports the ability to set the bit rate as +well as number of data- and stop bits by writing to control addresses +via the control interface. + + |