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| -rw-r--r-- | README.md | 5 |
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@@ -6,4 +6,9 @@ A Universal asynchronous receiver/transmitter (UART) implemented in Verilog. This UART used to be in coretest, but has been moved out as a separate project. +The current implementation supports the ability to set the bit rate as +well as number of data- and stop bits by writing to control addresses +via the control interface. + + |