From 10fb68d2e111502ecfd86083b3f8143b661d0406 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 9 May 2014 13:14:17 +0200 Subject: Adding a note about the new ability to change bit rate as well as number of data- and stop bits. --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 5361cd0..513ccf0 100644 --- a/README.md +++ b/README.md @@ -6,4 +6,9 @@ A Universal asynchronous receiver/transmitter (UART) implemented in Verilog. This UART used to be in coretest, but has been moved out as a separate project. +The current implementation supports the ability to set the bit rate as +well as number of data- and stop bits by writing to control addresses +via the control interface. + + -- cgit v1.2.3