| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | cdc_bus_pulse.v | 5463 | logplainblame |
| -rw-r--r-- | fmc_arbiter.v | 11116 | logplainblame |
| -rw-r--r-- | fmc_arbiter_cdc.v | 5288 | logplainblame |
| -rw-r--r-- | fmc_d_phy.v | 2906 | logplainblame |
| -rw-r--r-- | fmc_indicator.v | 2623 | logplainblame |
| -rw-r--r-- | fmc_regs.v | 4428 | logplainblame |
 |
index : core/comm/fmc | |
| Verilog implementation of Flexible Memory Controller interface used to connect FPGA cores to STM32 MCU | git repositories |
| aboutsummaryrefslogtreecommitdiff |