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-rw-r--r--src/rtl/fmc_arbiter_cdc.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/fmc_arbiter_cdc.v b/src/rtl/fmc_arbiter_cdc.v
index 0eca0b1..63e65b5 100644
--- a/src/rtl/fmc_arbiter_cdc.v
+++ b/src/rtl/fmc_arbiter_cdc.v
@@ -113,12 +113,12 @@ module fmc_arbiter_cdc #
//
- // System Request 1-cycle delay to compensate registered mux delay in user-side logic
+ // System Request 2-cycle delay to compensate registered mux delay in user-side logic
//
- reg sys_req_dly = 1'b0;
+ reg [ 1: 0] sys_req_dly = 2'b00;
always @(posedge sys_clk)
- sys_req_dly <= sys_req;
+ sys_req_dly <= {sys_req_dly[0], sys_req};
//
// SYS_CLK -> FMC_CLK Acknowledge
@@ -131,7 +131,7 @@ module fmc_arbiter_cdc #
(
.src_clk(sys_clk),
.src_din(sys_data_in),
- .src_req(sys_req_dly),
+ .src_req(sys_req_dly[1]),
.dst_clk(fmc_clk),
.dst_dout(fmc_dout),