core/comm/fmc - Verilog implementation of Flexible Memory Controller interface used to connect FPGA cores to STM32 MCU

Age	Commit message (Expand)	Author
2021-07-19	Fixed copyright notices.HEAD master	Pavel V. Shatov (Meister)
2021-04-12	Updated testbench to match how things work in hardware.	Pavel V. Shatov (Meister)
2020-01-21	Another testbench to make sure, that the new pipelined core selector can	Pavel V. Shatov (Meister)
2020-01-21	New testbench with two clocks.	Pavel V. Shatov (Meister)
2020-01-21	Bumped version number.	Pavel V. Shatov (Meister)
2020-01-21	New FMC arbiter. FMC bus now runs at 45 MHz, while the system clock is 90 MHz,	Pavel V. Shatov (Meister)
2018-07-06	Forgot to bump version number.	Pavel V. Shatov (Meister)
2018-07-05	Added testbench to mimic STM32's FMC side.	Pavel V. Shatov (Meister)
2018-07-05	FMC arbiter overhaul.	Pavel V. Shatov (Meister)
2018-07-05	Removed now unnecessary CDC modules.	Pavel V. Shatov (Meister)
2015-11-12	Merge branch 'modexps6'	Paul Selkirk
2015-11-12	Change reset to active-low.	Paul Selkirk
2015-10-31	2-cycle sys_req delay for modexps6, because block RAMs	Paul Selkirk
2015-10-29	Initial commit	Paul Selkirk