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2021-07-19Fixed copyright notices.HEADmasterPavel V. Shatov (Meister)
2021-04-12Updated testbench to match how things work in hardware.Pavel V. Shatov (Meister)
2020-01-21Another testbench to make sure, that the new pipelined core selector canPavel V. Shatov (Meister)
2020-01-21New testbench with two clocks.Pavel V. Shatov (Meister)
2020-01-21Bumped version number.Pavel V. Shatov (Meister)
2020-01-21New FMC arbiter. FMC bus now runs at 45 MHz, while the system clock is 90 MHz,Pavel V. Shatov (Meister)
2018-07-06Forgot to bump version number.Pavel V. Shatov (Meister)
2018-07-05Added testbench to mimic STM32's FMC side.Pavel V. Shatov (Meister)
2018-07-05FMC arbiter overhaul.Pavel V. Shatov (Meister)
2018-07-05Removed now unnecessary CDC modules.Pavel V. Shatov (Meister)
2015-11-12Merge branch 'modexps6'Paul Selkirk
2015-11-12Change reset to active-low.Paul Selkirk
2015-10-312-cycle sys_req delay for modexps6, because block RAMsPaul Selkirk
2015-10-29Initial commitPaul Selkirk