| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | cdc_bus_pulse.v | 5463 | logplainblame |
| -rw-r--r-- | eim.v | 3872 | logplainblame |
| -rw-r--r-- | eim_arbiter.v | 11021 | logplainblame |
| -rw-r--r-- | eim_arbiter_cdc.v | 4883 | logplainblame |
| -rw-r--r-- | eim_da_phy.v | 2912 | logplainblame |
| -rw-r--r-- | eim_indicator.v | 2623 | logplainblame |
| -rw-r--r-- | eim_regs.v | 4432 | logplainblame |
 |
index : core/comm/eim | |
| Verilog implementation of EIM interface used to connect FPGA cores to Freescale i | git repositories |
| aboutsummaryrefslogtreecommitdiff |