| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | LICENSE | 1481 | logplainblame |
| -rw-r--r-- | README.md | 108 | logplainblame |
| d--------- | src / rtl | 30 | logplain |
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index : core/comm/eim | |
| Verilog implementation of EIM interface used to connect FPGA cores to Freescale i | git repositories |
| aboutsummaryrefslogtreecommitdiff |