core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Branch	Commit message	Author	Age
cleanup	(1) Cleanup of top an core code with no functional changes. The code is now m...	Joachim Strömbergson	7 years
master	(1) Removed reset input port from qr module, qr module instances and qr modul...	Joachim Strömbergson	5 years
timing_fix	Debugged pipeline register and state update. All test cases ok.	Joachim Strömbergson	6 years


Age	Commit message	Author
2018-08-23	Debugged pipeline register and state update. All test cases ok.timing_fix	Joachim Strömbergson
2018-08-23	Added missing define.	Joachim Strömbergson
2018-08-23	(1) Adding pipeline register update code and a set of pipeline registers. Reg...	Joachim Strömbergson
2018-08-23	(1) Updated qr interface to include clock and reset needed for internal pipel...	Joachim Strömbergson
2016-12-28	(1) Cleanup of top an core code with no functional changes. The code is now m...cleanup	Joachim Strömbergson
2015-04-30	(1) Added api addresses and constants for core name and version. (2) Changed ...	Joachim Strömbergson
2014-11-06	Fixes to nits found using the verilator linter.	Joachim Strömbergson
2014-09-26	Update of ChaCha with fixes found during synthesis.	Joachim Strömbergson
2014-09-03	Adding Makefile for building and running chacha simulations.	Joachim Strömbergson
2014-09-03	Adding a Python functional model of the ChaCha stream cipher.	Joachim Strömbergson
[...]

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