core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Branch	Commit message	Author	Age
cleanup	(1) Cleanup of top an core code with no functional changes. The code is now m...	Joachim Strömbergson	8 years
master	(1) Removed reset input port from qr module, qr module instances and qr modul...	Joachim Strömbergson	6 years
timing_fix	Debugged pipeline register and state update. All test cases ok.	Joachim Strömbergson	6 years


Age	Commit message	Author
2019-02-08	(1) Removed reset input port from qr module, qr module instances and qr modul...HEAD master	Joachim Strömbergson
2019-02-07	Change reset to asynch assert. This matches comment. It also matches what is ...	Joachim Strömbergson
2018-10-23	Hardening the API to block writes to contol signals when core is performing o...	Joachim Strömbergson
2018-10-16	Adding width specification, fixed order and other nits as part of ceckning th...	Joachim Strömbergson
2018-08-30	Adding two more pipeline registers in the qr module. Added two more wait cycles.	Joachim Strömbergson
2018-08-23	Debugged pipeline register and state update. All test cases ok.timing_fix	Joachim Strömbergson
2018-08-23	Added missing define.	Joachim Strömbergson
2018-08-23	(1) Adding pipeline register update code and a set of pipeline registers. Reg...	Joachim Strömbergson
2018-08-23	(1) Updated qr interface to include clock and reset needed for internal pipel...	Joachim Strömbergson
2016-12-28	(1) Cleanup of top an core code with no functional changes. The code is now m...cleanup	Joachim Strömbergson
[...]

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