(1) Adding pipeline register update code and a set of pipeline registers. Registers are not connected at the this stage. (2) Added self testing tetst cases and debug outputs to observe internal behaviour.

2 files changed, 47 insertions, 7 deletions

diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index e1ddbd8..5189030 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -59,6 +59,10 @@ module chacha_qr(
   //----------------------------------------------------------------
   reg [31 : 0] a0_reg;
   reg [31 : 0] a0_new;
+//  reg [31 : 0] a1_reg;
+//  reg [31 : 0] a1_new;
+//  reg [31 : 0] c0_reg;
+//  reg [31 : 0] c0_new;
 
 
   //----------------------------------------------------------------
@@ -87,11 +91,15 @@ module chacha_qr(
       if (!reset_n)
         begin
           a0_reg <= 32'h0;
+//          a1_reg <= 32'h0;
+//          c0_reg <= 32'h0;
         end
 
       else
         begin
           a0_reg <= a0_new;
+//          a1_reg <= a1_new;
+//          c0_reg <= c0_new;
         end
     end // reg_update
 
@@ -120,14 +128,20 @@ module chacha_qr(
       reg [31 : 0] d3;
 
       a0 = a + b;
-      a0_new = a + b;
+      a0_new = a0;
 
       d0 = d ^ a0;
       d1 = {d0[15 : 0], d0[31 : 16]};
+
       c0 = c + d1;
+//      c0_new = c0;
+
       b0 = b ^ c0;
       b1 = {b0[19 : 0], b0[31 : 20]};
+
       a1 = a0 + b1;
+//      a1_new = a1;
+
       d2 = d1 ^ a1;
       d3 = {d2[23 : 0], d2[31 : 24]};
       c1 = c0 + d3;
diff --git a/src/tb/tb_chacha_qr.v b/src/tb/tb_chacha_qr.v
index 66a790c..06759d7 100644
--- a/src/tb/tb_chacha_qr.v
+++ b/src/tb/tb_chacha_qr.v
@@ -114,12 +114,21 @@ module tb_chacha_qr();
       cycle_ctr = cycle_ctr + 1;
 
       $display("cycle = %08x:", cycle_ctr);
-      $display("");
-
-      $display("a      = %08x, b      = %08x, c      = %08x, d      = %08x",
+      $display("a      = 0x%08x, b      = 0x%08x, c      = 0x%08x, d      = 0x%08x",
                a, b, c, d);
-      $display("a_prim = %08x, b_prim = %08x, c_prim = %08x, d_prim = %08x",
+      $display("a_prim = 0x%08x, b_prim = 0x%08x, c_prim = 0x%08x, d_prim = 0x%08x",
                a_prim, b_prim, c_prim, d_prim);
+      $display("a0     = 0x%08x, a1     = 0x%08x",
+               dut.qr.a0, dut.qr.a1);
+      $display("b0     = 0x%08x, b1     = 0x%08x, b2     = 0x%08x, b3     = 0x%08x",
+               dut.qr.b0, dut.qr.b1, dut.qr.b2, dut.qr.b3);
+      $display("c0     = 0x%08x, c1     = 0x%08x",
+               dut.qr.c0, dut.qr.c1);
+      $display("d0     = 0x%08x, d1     = 0x%08x, d2     = 0x%08x, d3     = 0x%08x",
+               dut.qr.d0, dut.qr.d1, dut.qr.d2, dut.qr.d3);
+      $display("a0_reg = 0x%08x", dut.a0_reg);
+//      $display("a1_reg = 0x%08x", dut.a1_reg);
+//      $display("c0_reg = 0x%08x", dut.c0_reg);
       $display("");
     end // dut_monitor
 
@@ -167,19 +176,36 @@ module tb_chacha_qr();
     begin
       $display("*** Test of Quarterround:");
       $display("");
+
+      $display("First test:");
       a = 32'h11223344;
       b = 32'h11223344;
       c = 32'h11223344;
       d = 32'h11223344;
-
       #(CLK_PERIOD * 10);
+      $display("");
 
+      if (a_prim == 32'he7a34e04 && b_prim == 32'h9a971009 &&
+          c_prim == 32'hd66bc95c && d_prim == 32'h6f7d62b2)
+        $display("Ok: First test case correct.");
+      else
+        $display("Error: Expected a_prim = e7a34e04, b_prim = 9a971009, c_prim = d66bc95c, d_prim = 6f7d62b2");
+      $display("");
+
+
+      $display("Second test:");
       a = 32'h55555555;
       b = 32'h55555555;
       c = 32'h55555555;
       d = 32'h55555555;
-
       #(CLK_PERIOD * 10);
+
+      if (a_prim == 32'haaaabaaa && b_prim == 32'h4d5d54d5 &&
+          c_prim == 32'haa9aaaa9 && d_prim == 32'h55455555)
+        $display("Ok: Second test case correct.");
+      else
+        $display("Error: Expected a_prim = aaaabaaa, b_prim = 4d5d54d5, c_prim = aa9aaaa9, d_prim = 55455555");
+
     end
   endtask // qr_tests