core/cipher/aes_speed - (Old) Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Branch	Commit message	Author	Age
master	Adding restriction to the API to only allow writes to controlling registers. ...	Joachim Strömbergson	6 years


Age	Commit message	Author
2018-10-03	Adding restriction to the API to only allow writes to controlling registers. ...HEAD master	Joachim Strömbergson
2018-10-03	Adding testcase that tests the mangling of aes operations by switching from e...	Joachim Strömbergson
2018-10-02	Reading AES result will be zero when ready is not set.	Joachim Strömbergson
2018-09-27	Added missing reset of registers. This fixes CT-01-001 FPGA.	Joachim Strömbergson
2018-05-26	Shaved off another cycle for block processing.	Joachim Strömbergson
2018-05-22	Updated README with latest implementation results and status for the core.	Joachim Strömbergson
2018-05-22	Minor cleanup of states and register sizes.	Joachim Strömbergson
2018-05-22	Combined all AES round operations into a single operation for a round.	Joachim Strömbergson
2018-05-22	Polished the wait_ready task to use defined bit index.	Joachim Strömbergson
2018-05-22	Updated README with implementation results.	Joachim Strömbergson
[...]

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