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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
| commit | 9af80907f9d1913cd8cb200eabe5e99cc65021a4 (patch) | |
| tree | afeb4ec1491932a0f9e42b8efde28f8c85e887a8 | |
| parent | c1225cb6c9843e91f3b3dfee294fc1f9309e8212 (diff) | |
Added missing reset of registers. This fixes CT-01-001 FPGA.
| -rw-r--r-- | src/rtl/aes_key_mem.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v index e3aec4b..07e338f 100644 --- a/src/rtl/aes_key_mem.v +++ b/src/rtl/aes_key_mem.v @@ -140,12 +140,14 @@ module aes_key_mem( if (!reset_n) begin - for (i = 0 ; i < 4 ; i = i + 1) + for (i = 0 ; i < 15 ; i = i + 1) key_mem [i] <= 128'h0; rcon_reg <= 8'h0; ready_reg <= 1'b0; round_ctr_reg <= 4'h0; + prev_key0_reg <= 128'h0; + prev_key1_reg <= 128'h0; key_mem_ctrl_reg <= CTRL_IDLE; end else |