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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-03 09:15:14 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-03 09:15:14 +0200 |
| commit | 963e729eb9dd4c85b86ebd504d60e54c35e653f3 (patch) | |
| tree | 05ba16c8ffb3b76943a40486d9603e87c46b0f79 | |
| parent | 01d3fb3564043b032764deb1739c199ee867b77f (diff) | |
Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA.HEADmaster
| -rw-r--r-- | src/rtl/aes.v | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v index 48a7735..492ba56 100644 --- a/src/rtl/aes.v +++ b/src/rtl/aes.v @@ -225,20 +225,23 @@ module aes( begin if (we) begin - if (address == ADDR_CTRL) + if (core_ready) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; - end + if (address == ADDR_CTRL) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + end - if (address == ADDR_CONFIG) - config_we = 1'b1; + if (address == ADDR_CONFIG) + config_we = 1'b1; - if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) - key_we = 1'b1; + if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) + key_we = 1'b1; - if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) - block_we = 1'b1; + if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) + block_we = 1'b1; + end end // if (we) else |