core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Expand)	Author
2018-06-14	Added CC_FLAGS and LINT_FLAGS.	Joachim Strömbergson
2018-05-22	Added missing implementation results for Xilinx Artix7.	Joachim Strömbergson
2018-05-22	Added wait_ready task to allow test cases to wait for the core to complete an...	Joachim Strömbergson
2017-12-15	Adding the error port that went missing. Sloppy.	Joachim Strömbergson
2017-12-14	Synced the AES core rtl and testbench to github. The updates does not add or ...	Joachim Strömbergson
2017-12-14	Adding support for linting the AES core.	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-10-02	Fixing text error in comment.	Joachim Strömbergson
2015-07-17	fix CORE_VERSION to match what we think it should be	Paul Selkirk
2015-05-28	Corrected where config bits are.	Joachim Strömbergson
2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ...	Joachim Strömbergson
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have i...	Joachim Strömbergson
2014-11-28	Reworked the sbox and inverse sbox. Slighly smaller design and much shorter s...	Joachim Strömbergson
2014-11-28	Removed obsolete target.	Joachim Strömbergson
2014-11-27	Adding Makefile for building simulation targets.	Joachim Strömbergson
2014-11-27	Adding Python models for AES as well as key expansion and rcon.	Joachim Strömbergson
2014-11-27	Adding testbenchs.	Joachim Strömbergson
2014-11-27	Adding RTL source files for the AES core.	Joachim Strömbergson
2014-11-27	Adding license file too.	Joachim Strömbergson
2014-11-27	Adding readme for the aes core.	Joachim Strömbergson