Adding RTL source files for the AES core.

author: Joachim Strömbergson <joachim@secworks.se> 2014-11-27 15:48:42 +0100
committer: Joachim Strömbergson <joachim@secworks.se> 2014-11-27 15:48:42 +0100
commit: 1ecc3b5ccceda62110c20c55683167ce9ab3cf99 (patch)
tree: bd3301e4e9ca0bf49e9bd521502700430a514511
parent: be15776087991ae3f2f7874f67c79256c11016aa (diff)
7 files changed, 4725 insertions, 0 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
new file mode 100644
index 0000000..2ead578
--- /dev/null
+++ b/src/rtl/aes.v
@@ -0,0 +1,586 @@
+//======================================================================
+//
+// aes.v
+// --------
+// Top level wrapper for the AES block cipher core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes(
+           // Clock and reset.
+           input wire           clk,
+           input wire           reset_n,
+
+           // Control.
+           input wire           cs,
+           input wire           we,
+
+           // Data ports.
+           input wire  [7 : 0]  address,
+           input wire  [31 : 0] write_data,
+           output wire [31 : 0] read_data,
+           output wire          error
+          );
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter ADDR_NAME0       = 8'h00;
+  parameter ADDR_NAME1       = 8'h01;
+  parameter ADDR_VERSION     = 8'h02;
+
+  parameter ADDR_CTRL        = 8'h08;
+  parameter CTRL_INIT_BIT    = 0;
+  parameter CTRL_NEXT_BIT    = 1;
+
+  parameter ADDR_CONFIG      = 8'h09;
+  parameter CTRL_ENCDEC_BIT  = 0;
+  parameter CTRL_KEYLEN_BIT  = 1;
+
+  parameter ADDR_STATUS      = 8'h0a;
+  parameter STATUS_READY_BIT = 0;
+  parameter STATUS_VALID_BIT = 1;
+
+  parameter ADDR_KEY0        = 8'h10;
+  parameter ADDR_KEY1        = 8'h11;
+  parameter ADDR_KEY2        = 8'h12;
+  parameter ADDR_KEY3        = 8'h13;
+  parameter ADDR_KEY4        = 8'h14;
+  parameter ADDR_KEY5        = 8'h15;
+  parameter ADDR_KEY6        = 8'h16;
+  parameter ADDR_KEY7        = 8'h17;
+
+  parameter ADDR_BLOCK0      = 8'h20;
+  parameter ADDR_BLOCK1      = 8'h21;
+  parameter ADDR_BLOCK2      = 8'h22;
+  parameter ADDR_BLOCK3      = 8'h23;
+
+  parameter ADDR_RESULT0     = 8'h30;
+  parameter ADDR_RESULT1     = 8'h31;
+  parameter ADDR_RESULT2     = 8'h32;
+  parameter ADDR_RESULT3     = 8'h33;
+
+  parameter CORE_NAME0       = 32'h6165732d; // "aes-"
+  parameter CORE_NAME1       = 32'h31323820; // "128 "
+  parameter CORE_VERSION     = 32'h302e3530; // "0.50"
+
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg init_reg;
+  reg init_new;
+  reg init_we;
+  reg init_set;
+
+  reg next_reg;
+  reg next_new;
+  reg next_we;
+  reg next_set;
+
+  reg encdec_reg;
+  reg keylen_reg;
+  reg config_we;
+
+  reg [31 : 0] block0_reg;
+  reg          block0_we;
+  reg [31 : 0] block1_reg;
+  reg          block1_we;
+  reg [31 : 0] block2_reg;
+  reg          block2_we;
+  reg [31 : 0] block3_reg;
+  reg          block3_we;
+
+  reg [31 : 0] key0_reg;
+  reg          key0_we;
+  reg [31 : 0] key1_reg;
+  reg          key1_we;
+  reg [31 : 0] key2_reg;
+  reg          key2_we;
+  reg [31 : 0] key3_reg;
+  reg          key3_we;
+  reg [31 : 0] key4_reg;
+  reg          key4_we;
+  reg [31 : 0] key5_reg;
+  reg          key5_we;
+  reg [31 : 0] key6_reg;
+  reg          key6_we;
+  reg [31 : 0] key7_reg;
+  reg          key7_we;
+
+  reg [127 : 0] result_reg;
+  reg           valid_reg;
+  reg           ready_reg;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [31 : 0]   tmp_read_data;
+  reg            tmp_error;
+
+  wire           core_encdec;
+  wire           core_init;
+  wire           core_next;
+  wire           core_ready;
+  wire [255 : 0] core_key;
+  wire           core_keylen;
+  wire [127 : 0] core_block;
+  wire [127 : 0] core_result;
+  wire           core_valid;
+
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign read_data = tmp_read_data;
+  assign error     = tmp_error;
+
+  assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg,
+                     key4_reg, key5_reg, key6_reg, key7_reg};
+
+  assign core_block  = {block0_reg, block1_reg, block2_reg, block3_reg};
+  assign core_init   = init_reg;
+  assign core_next   = next_reg;
+  assign core_encdec = encdec_reg;
+  assign core_keylen = keylen_reg;
+
+
+  //----------------------------------------------------------------
+  // core instantiation.
+  //----------------------------------------------------------------
+  aes_core core(
+                .clk(clk),
+                .reset_n(reset_n),
+
+                .encdec(core_encdec),
+                .init(core_init),
+                .next(core_next),
+                .ready(core_ready),
+
+                .key(core_key),
+                .keylen(core_keylen),
+
+                .block(core_block),
+                .result(core_result),
+                .result_valid(core_valid)
+               );
+
+
+  //----------------------------------------------------------------
+  // reg_update
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with asynchronous
+  // active low reset.
+  //----------------------------------------------------------------
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        begin
+          block0_reg <= 32'h00000000;
+          block1_reg <= 32'h00000000;
+          block2_reg <= 32'h00000000;
+          block3_reg <= 32'h00000000;
+
+          key0_reg   <= 32'h00000000;
+          key1_reg   <= 32'h00000000;
+          key2_reg   <= 32'h00000000;
+          key3_reg   <= 32'h00000000;
+          key4_reg   <= 32'h00000000;
+          key5_reg   <= 32'h00000000;
+          key6_reg   <= 32'h00000000;
+          key7_reg   <= 32'h00000000;
+
+          init_reg   <= 0;
+          next_reg   <= 0;
+          encdec_reg <= 0;
+          keylen_reg <= 0;
+
+          result_reg <= 128'h00000000000000000000000000000000;
+          valid_reg  <= 0;
+          ready_reg  <= 0;
+        end
+      else
+        begin
+          ready_reg      <= core_ready;
+          valid_reg      <= core_valid;
+          result_reg     <= core_result;
+
+          if (init_we)
+            begin
+              init_reg <= init_new;
+            end
+
+          if (next_we)
+            begin
+              next_reg <= next_new;
+            end
+
+          if (config_we)
+            begin
+              encdec_reg <= write_data[CTRL_ENCDEC_BIT];
+              keylen_reg <= write_data[CTRL_KEYLEN_BIT];
+            end
+
+          if (key0_we)
+            begin
+              key0_reg <= write_data;
+            end
+
+          if (key1_we)
+            begin
+              key1_reg <= write_data;
+            end
+
+          if (key2_we)
+            begin
+              key2_reg <= write_data;
+            end
+
+          if (key3_we)
+            begin
+              key3_reg <= write_data;
+            end
+
+          if (key4_we)
+            begin
+              key4_reg <= write_data;
+            end
+
+          if (key5_we)
+            begin
+              key5_reg <= write_data;
+            end
+
+          if (key6_we)
+            begin
+              key6_reg <= write_data;
+            end
+
+          if (key7_we)
+            begin
+              key7_reg <= write_data;
+            end
+
+          if (block0_we)
+            begin
+              block0_reg <= write_data;
+            end
+
+          if (block1_we)
+            begin
+              block1_reg <= write_data;
+            end
+
+          if (block2_we)
+            begin
+              block2_reg <= write_data;
+            end
+
+          if (block3_we)
+            begin
+              block3_reg <= write_data;
+            end
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // flag_ctrl
+  //
+  // Logic to set and the automatically reset init- and
+  // next flags that has been set.
+  //----------------------------------------------------------------
+  always @*
+    begin : flag_reset
+      init_new = 0;
+      init_we  = 0;
+      next_new = 0;
+      next_we  = 0;
+
+      if (init_set)
+        begin
+          init_new = 1;
+          init_we  = 1;
+        end
+      else if (init_reg)
+        begin
+          init_new = 0;
+          init_we  = 1;
+        end
+
+      if (next_set)
+        begin
+          next_new = 1;
+          next_we  = 1;
+        end
+      else if (next_reg)
+        begin
+          next_new = 0;
+          next_we  = 1;
+        end
+    end
+
+
+  //----------------------------------------------------------------
+  // api
+  //
+  // The interface command decoding logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : api
+      init_set      = 0;
+      next_set      = 0;
+      config_we     = 0;
+      key0_we       = 0;
+      key1_we       = 0;
+      key2_we       = 0;
+      key3_we       = 0;
+      key4_we       = 0;
+      key5_we       = 0;
+      key6_we       = 0;
+      key7_we       = 0;
+      block0_we     = 0;
+      block1_we     = 0;
+      block2_we     = 0;
+      block3_we     = 0;
+      tmp_read_data = 32'h00000000;
+      tmp_error     = 0;
+
+      if (cs)
+        begin
+          if (we)
+            begin
+              case (address)
+                // Write operations.
+                ADDR_CTRL:
+                  begin
+                    init_set = write_data[CTRL_INIT_BIT];
+                    next_set = write_data[CTRL_NEXT_BIT];
+                  end
+
+                ADDR_CONFIG:
+                  begin
+                    config_we = 1;
+                  end
+
+                ADDR_KEY0:
+                  begin
+                    key0_we = 1;
+                  end
+
+                ADDR_KEY1:
+                  begin
+                    key1_we = 1;
+                  end
+
+                ADDR_KEY2:
+                  begin
+                    key2_we = 1;
+                  end
+
+                ADDR_KEY3:
+                  begin
+                    key3_we = 1;
+                  end
+
+                ADDR_KEY4:
+                  begin
+                    key4_we = 1;
+                  end
+
+                ADDR_KEY5:
+                  begin
+                    key5_we = 1;
+                  end
+
+                ADDR_KEY6:
+                  begin
+                    key6_we = 1;
+                  end
+
+                ADDR_KEY7:
+                  begin
+                    key7_we = 1;
+                  end
+
+                ADDR_BLOCK0:
+                  begin
+                    block0_we = 1;
+                  end
+
+                ADDR_BLOCK1:
+                  begin
+                    block1_we = 1;
+                  end
+
+                ADDR_BLOCK2:
+                  begin
+                    block2_we = 1;
+                  end
+
+                ADDR_BLOCK3:
+                  begin
+                    block3_we = 1;
+                  end
+
+                default:
+                  begin
+                    tmp_error = 1;
+                  end
+              endcase // case (address)
+            end // if (we)
+
+          else
+            begin
+              case (address)
+                // Read operations.
+                ADDR_NAME0:
+                  begin
+                    tmp_read_data = CORE_NAME0;
+                  end
+
+                ADDR_NAME1:
+                  begin
+                    tmp_read_data = CORE_NAME1;
+                  end
+
+                ADDR_VERSION:
+                  begin
+                    tmp_read_data = CORE_VERSION;
+                  end
+
+                ADDR_CTRL:
+                  begin
+                    tmp_read_data = {28'h0000000, keylen_reg, encdec_reg,
+                                     next_reg, init_reg};
+                  end
+
+                ADDR_STATUS:
+                  begin
+                    tmp_read_data = {30'h00000000, valid_reg, ready_reg};
+                  end
+
+                ADDR_KEY0:
+                  begin
+                    tmp_read_data = key0_reg;
+                  end
+
+                ADDR_KEY1:
+                  begin
+                    tmp_read_data = key1_reg;
+                  end
+
+                ADDR_KEY2:
+                  begin
+                    tmp_read_data = key2_reg;
+                  end
+
+                ADDR_KEY3:
+                  begin
+                    tmp_read_data = key3_reg;
+                  end
+
+                ADDR_KEY4:
+                  begin
+                    tmp_read_data = key4_reg;
+                  end
+
+                ADDR_KEY5:
+                  begin
+                    tmp_read_data = key5_reg;
+                  end
+
+                ADDR_KEY6:
+                  begin
+                    tmp_read_data = key6_reg;
+                  end
+
+                ADDR_KEY7:
+                  begin
+                    tmp_read_data = key7_reg;
+                  end
+
+                ADDR_BLOCK0:
+                  begin
+                    tmp_read_data = block0_reg;
+                  end
+
+                ADDR_BLOCK1:
+                  begin
+                    tmp_read_data = block1_reg;
+                  end
+
+                ADDR_BLOCK2:
+                  begin
+                    tmp_read_data = block2_reg;
+                  end
+
+                ADDR_BLOCK3:
+                  begin
+                    tmp_read_data = block3_reg;
+                  end
+
+                ADDR_RESULT0:
+                  begin
+                    tmp_read_data = result_reg[127 : 96];
+                  end
+
+                ADDR_RESULT1:
+                  begin
+                    tmp_read_data = result_reg[95 : 64];
+                  end
+
+                ADDR_RESULT2:
+                  begin
+                    tmp_read_data = result_reg[63 : 32];
+                  end
+
+                ADDR_RESULT3:
+                  begin
+                    tmp_read_data = result_reg[31 : 0];
+                  end
+
+                default:
+                  begin
+                    tmp_error = 1;
+                  end
+              endcase // case (address)
+            end
+        end
+    end // addr_decoder
+endmodule // aes
+
+//======================================================================
+// EOF aes.v
+//======================================================================
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v
new file mode 100644
index 0000000..c43c943
--- /dev/null
+++ b/src/rtl/aes_core.v
@@ -0,0 +1,344 @@
+//======================================================================
+//
+// aes.core.v
+// ----------
+// The AES core. This core supports key size of 128, and 256 bits.
+// Most of the functionality is within the submodules.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_core(
+                input wire            clk,
+                input wire            reset_n,
+
+                input wire            encdec,
+                input wire            init,
+                input wire            next,
+                output wire           ready,
+
+                input wire [255 : 0]  key,
+                input wire            keylen,
+
+                input wire [127 : 0]  block,
+                output wire [127 : 0] result,
+                output wire           result_valid
+               );
+
+
+
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter CTRL_IDLE  = 2'h0;
+  parameter CTRL_INIT  = 2'h1;
+  parameter CTRL_NEXT  = 2'h2;
+
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [1 : 0] aes_core_ctrl_reg;
+  reg [1 : 0] aes_core_ctrl_new;
+  reg         aes_core_ctrl_we;
+
+  reg         result_valid_reg;
+  reg         result_valid_new;
+  reg         result_valid_we;
+
+  reg         ready_reg;
+  reg         ready_new;
+  reg         ready_we;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg            init_state;
+
+  wire [127 : 0] round_key;
+  wire           key_ready;
+
+  reg            enc_next;
+  wire [3 : 0]   enc_round_nr;
+  wire [127 : 0] enc_new_block;
+  wire           enc_ready;
+  wire [31 : 0]  enc_sboxw;
+
+  reg            dec_next;
+  wire [3 : 0]   dec_round_nr;
+  wire [127 : 0] dec_new_block;
+  wire           dec_ready;
+
+  reg [127 : 0]  muxed_new_block;
+  reg [3 : 0]    muxed_round_nr;
+  reg            muxed_ready;
+
+  wire [31 : 0]  keymem_sboxw;
+
+  reg [31 : 0]   muxed_sboxw;
+  wire [31 : 0]  new_sboxw;
+
+
+  //----------------------------------------------------------------
+  // Instantiations.
+  //----------------------------------------------------------------
+  aes_encipher_block enc_block(
+                               .clk(clk),
+                               .reset_n(reset_n),
+
+                               .next(enc_next),
+
+                               .keylen(keylen),
+                               .round(enc_round_nr),
+                               .round_key(round_key),
+
+                               .sboxw(enc_sboxw),
+                               .new_sboxw(new_sboxw),
+
+                               .block(block),
+                               .new_block(enc_new_block),
+                               .ready(enc_ready)
+                              );
+
+
+  aes_decipher_block dec_block(
+                               .clk(clk),
+                               .reset_n(reset_n),
+
+                               .next(dec_next),
+
+                               .keylen(keylen),
+                               .round(dec_round_nr),
+                               .round_key(round_key),
+
+                               .block(block),
+                               .new_block(dec_new_block),
+                               .ready(dec_ready)
+                              );
+
+
+  aes_key_mem keymem(
+                     .clk(clk),
+                     .reset_n(reset_n),
+
+                     .key(key),
+                     .keylen(keylen),
+                     .init(init),
+
+                     .round(muxed_round_nr),
+                     .round_key(round_key),
+                     .ready(key_ready),
+
+                     .sboxw(keymem_sboxw),
+                     .new_sboxw(new_sboxw)
+                    );
+
+
+  aes_sbox sbox(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
+
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign ready        = ready_reg;
+  assign result       = muxed_new_block;
+  assign result_valid = result_valid_reg;
+
+
+  //----------------------------------------------------------------
+  // reg_update
+  //
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with asynchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk or negedge reset_n)
+    begin: reg_update
+      if (!reset_n)
+        begin
+          result_valid_reg  <= 1'b0;
+          ready_reg         <= 1'b1;
+          aes_core_ctrl_reg <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (result_valid_we)
+            begin
+              result_valid_reg <= result_valid_new;
+            end
+
+          if (ready_we)
+            begin
+              ready_reg <= ready_new;
+            end
+
+          if (aes_core_ctrl_we)
+            begin
+              aes_core_ctrl_reg <= aes_core_ctrl_new;
+            end
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // sbox_mux
+  //
+  // Controls which of the encipher datapath or the key memory
+  // that gets access to the sbox.
+  //----------------------------------------------------------------
+  always @*
+    begin : sbox_mux
+      if (init_state)
+        begin
+          muxed_sboxw = keymem_sboxw;
+        end
+      else
+        begin
+          muxed_sboxw = enc_sboxw;
+        end
+    end // sbox_mux
+
+
+  //----------------------------------------------------------------
+  // encdex_mux
+  //
+  // Controls which of the datapaths that get the next signal, have
+  // access to the memory as well as the block processing result.
+  //----------------------------------------------------------------
+  always @*
+    begin : encdec_mux
+      enc_next = 0;
+      dec_next = 0;
+
+      if (encdec)
+        begin
+          // Encipher operations
+          enc_next        = next;
+          muxed_round_nr  = enc_round_nr;
+          muxed_new_block = enc_new_block;
+          muxed_ready     = enc_ready;
+        end
+      else
+        begin
+          // Decipher operations
+          dec_next        = next;
+          muxed_round_nr  = dec_round_nr;
+          muxed_new_block = dec_new_block;
+          muxed_ready     = dec_ready;
+        end
+    end // encdec_mux
+
+
+  //----------------------------------------------------------------
+  // aes_core_ctrl
+  //
+  // Control FSM for aes core. Basically tracks if we are in
+  // key init, encipher or decipher modes and connects the
+  // different submodules to shared resources and interface ports.
+  //----------------------------------------------------------------
+  always @*
+    begin : aes_core_ctrl
+      init_state        = 0;
+      ready_new         = 0;
+      ready_we          = 0;
+      result_valid_new  = 0;
+      result_valid_we   = 0;
+      aes_core_ctrl_new = CTRL_IDLE;
+      aes_core_ctrl_we  = 0;
+
+      case (aes_core_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            if (init)
+              begin
+                init_state        = 1;
+                ready_new         = 0;
+                ready_we          = 1;
+                result_valid_new  = 0;
+                result_valid_we   = 1;
+                aes_core_ctrl_new = CTRL_INIT;
+                aes_core_ctrl_we  = 1;
+              end
+            else if (next)
+              begin
+                init_state        = 0;
+                ready_new         = 0;
+                ready_we          = 1;
+                result_valid_new  = 0;
+                result_valid_we   = 1;
+                aes_core_ctrl_new = CTRL_NEXT;
+                aes_core_ctrl_we  = 1;
+              end
+          end
+
+        CTRL_INIT:
+          begin
+            init_state = 1;
+
+            if (key_ready)
+              begin
+                ready_new         = 1;
+                ready_we          = 1;
+                aes_core_ctrl_new = CTRL_IDLE;
+                aes_core_ctrl_we  = 1;
+              end
+          end
+
+        CTRL_NEXT:
+          begin
+            init_state = 0;
+
+            if (muxed_ready)
+              begin
+                ready_new         = 1;
+                ready_we          = 1;
+                result_valid_new  = 1;
+                result_valid_we   = 1;
+                aes_core_ctrl_new = CTRL_IDLE;
+                aes_core_ctrl_we  = 1;
+             end
+          end
+
+        default:
+          begin
+
+          end
+      endcase // case (aes_core_ctrl_reg)
+
+    end // aes_core_ctrl
+endmodule // aes_core
+
+//======================================================================
+// EOF aes_core.v
+//======================================================================
diff --git a/src/rtl/aes_decipher_block.v b/src/rtl/aes_decipher_block.v
new file mode 100644
index 0000000..ebcd164
--- /dev/null
+++ b/src/rtl/aes_decipher_block.v
@@ -0,0 +1,542 @@
+//======================================================================
+//
+// aes_decipher_block.v
+// --------------------
+// The AES decipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// decciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_decipher_block(
+                          input wire            clk,
+                          input wire            reset_n,
+
+                          input wire            next,
+
+                          input wire            keylen,
+                          output wire [3 : 0]   round,
+                          input wire [127 : 0]  round_key,
+
+                          input wire [127 : 0]  block,
+                          output wire [127 : 0] new_block,
+                          output wire           ready
+                         );
+
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter AES_128_BIT_KEY = 1'h0;
+  parameter AES_256_BIT_KEY = 1'h1;
+
+  parameter AES128_ROUNDS = 4'ha;
+  parameter AES256_ROUNDS = 4'he;
+
+  parameter NO_UPDATE    = 3'h0;
+  parameter INIT_UPDATE  = 3'h1;
+  parameter SBOX_UPDATE  = 3'h2;
+  parameter MAIN_UPDATE  = 3'h3;
+  parameter FINAL_UPDATE = 3'h4;
+
+  parameter CTRL_IDLE  = 3'h0;
+  parameter CTRL_INIT  = 3'h1;
+  parameter CTRL_SBOX  = 3'h2;
+  parameter CTRL_MAIN  = 3'h3;
+  parameter CTRL_FINAL = 3'h4;
+
+
+  //----------------------------------------------------------------
+  // Gaolis multiplication functions for Inverse MixColumn.
+  //----------------------------------------------------------------
+  function [7 : 0] gm2(input [7 : 0] op);
+    begin
+      gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+    end
+  endfunction // gm2
+
+  function [7 : 0] gm3(input [7 : 0] op);
+    begin
+      gm3 = gm2(op) ^ op;
+    end
+  endfunction // gm3
+
+  function [7 : 0] gm4(input [7 : 0] op);
+    begin
+      gm4 = gm2(gm2(op));
+    end
+  endfunction // gm4
+
+  function [7 : 0] gm8(input [7 : 0] op);
+    begin
+      gm8 = gm2(gm4(op));
+    end
+  endfunction // gm8
+
+  function [7 : 0] gm09(input [7 : 0] op);
+    begin
+      gm09 = gm8(op) ^ op;
+    end
+  endfunction // gm09
+
+  function [7 : 0] gm11(input [7 : 0] op);
+    begin
+      gm11 = gm8(op) ^ gm2(op) ^ op;
+    end
+  endfunction // gm11
+
+  function [7 : 0] gm13(input [7 : 0] op);
+    begin
+      gm13 = gm8(op) ^ gm4(op) ^ op;
+    end
+  endfunction // gm13
+
+  function [7 : 0] gm14(input [7 : 0] op);
+    begin
+      gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
+    end
+  endfunction // gm14
+
+  function [31 : 0] inv_mixw(input [31 : 0] w);
+    reg [7 : 0] b0, b1, b2, b3;
+    reg [7 : 0] mb0, mb1, mb2, mb3;
+    begin
+      b0 = w[31 : 24];
+      b1 = w[23 : 16];
+      b2 = w[15 : 08];
+      b3 = w[07 : 00];
+
+      mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
+      mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
+      mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
+      mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
+
+      inv_mixw = {mb0, mb1, mb2, mb3};
+    end
+  endfunction // mixw
+
+  function [127 : 0] inv_mixcolumns(input [127 : 0] data);
+    reg [31 : 0] w0, w1, w2, w3;
+    reg [31 : 0] ws0, ws1, ws2, ws3;
+    begin
+      w0 = data[127 : 096];
+      w1 = data[095 : 064];
+      w2 = data[063 : 032];
+      w3 = data[031 : 000];
+
+      ws0 = inv_mixw(w0);
+      ws1 = inv_mixw(w1);
+      ws2 = inv_mixw(w2);
+      ws3 = inv_mixw(w3);
+
+      inv_mixcolumns = {ws0, ws1, ws2, ws3};
+    end
+  endfunction // inv_mixcolumns
+
+  function [127 : 0] inv_shiftrows(input [127 : 0] data);
+    reg [31 : 0] w0, w1, w2, w3;
+    reg [31 : 0] ws0, ws1, ws2, ws3;
+    begin
+      w0 = data[127 : 096];
+      w1 = data[095 : 064];
+      w2 = data[063 : 032];
+      w3 = data[031 : 000];
+
+      ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
+      ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
+      ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
+      ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
+
+      inv_shiftrows = {ws0, ws1, ws2, ws3};
+    end
+  endfunction // inv_shiftrows
+
+  function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+    begin
+      addroundkey = data ^ rkey;
+    end
+  endfunction // addroundkey
+
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [1 : 0]   sword_ctr_reg;
+  reg [1 : 0]   sword_ctr_new;
+  reg           sword_ctr_we;
+  reg           sword_ctr_inc;
+  reg           sword_ctr_rst;
+
+  reg [3 : 0]   round_ctr_reg;
+  reg [3 : 0]   round_ctr_new;
+  reg           round_ctr_we;
+  reg           round_ctr_set;
+  reg           round_ctr_dec;
+
+  reg [127 : 0] block_new;
+  reg [31 : 0]  block_w0_reg;
+  reg [31 : 0]  block_w1_reg;
+  reg [31 : 0]  block_w2_reg;
+  reg [31 : 0]  block_w3_reg;
+  reg           block_w0_we;
+  reg           block_w1_we;
+  reg           block_w2_we;
+  reg           block_w3_we;
+
+  reg           ready_reg;
+  reg           ready_new;
+  reg           ready_we;
+
+  reg [2 : 0]   dec_ctrl_reg;
+  reg [2 : 0]   dec_ctrl_new;
+  reg           dec_ctrl_we;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [31 : 0]  tmp_sboxw;
+  wire [31 : 0] new_sboxw;
+  reg [2 : 0]   update_type;
+  reg [3 : 0]   num_rounds;
+
+
+  //----------------------------------------------------------------
+  // Instantiations.
+  //----------------------------------------------------------------
+  aes_inv_sbox inv_sbox(.sword(tmp_sboxw), .new_sword(new_sboxw));
+
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign round     = round_ctr_reg;
+  assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+  assign ready     = ready_reg;
+
+
+  //----------------------------------------------------------------
+  // reg_update
+  //
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with synchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk or negedge reset_n)
+    begin: reg_update
+      if (!reset_n)
+        begin
+          block_w0_reg  <= 32'h00000000;
+          block_w1_reg  <= 32'h00000000;
+          block_w2_reg  <= 32'h00000000;
+          block_w3_reg  <= 32'h00000000;
+          sword_ctr_reg <= 2'h0;
+          round_ctr_reg <= 4'h0;
+          ready_reg     <= 1;
+          dec_ctrl_reg  <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (block_w0_we)
+            begin
+              block_w0_reg <= block_new[127 : 096];
+            end
+
+          if (block_w1_we)
+            begin
+              block_w1_reg <= block_new[095 : 064];
+            end
+
+          if (block_w2_we)
+            begin
+              block_w2_reg <= block_new[063 : 032];
+            end
+
+          if (block_w3_we)
+            begin
+              block_w3_reg <= block_new[031 : 000];
+            end
+
+          if (sword_ctr_we)
+            begin
+              sword_ctr_reg <= sword_ctr_new;
+            end
+
+          if (round_ctr_we)
+            begin
+              round_ctr_reg <= round_ctr_new;
+            end
+
+          if (ready_we)
+            begin
+              ready_reg <= ready_new;
+            end
+
+          if (dec_ctrl_we)
+            begin
+              dec_ctrl_reg <= dec_ctrl_new;
+            end
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // round_logic
+  //
+  // The logic needed to implement init, main and final rounds.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_logic
+      reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+      reg [127 : 0] addkey_block;
+
+      inv_shiftrows_block  = 128'h00000000000000000000000000000000;
+      inv_mixcolumns_block = 128'h00000000000000000000000000000000;
+      addkey_block         = 128'h00000000000000000000000000000000;
+      block_new            = 128'h00000000000000000000000000000000;
+      tmp_sboxw            = 32'h00000000;
+      block_w0_we          = 0;
+      block_w1_we          = 0;
+      block_w2_we          = 0;
+      block_w3_we          = 0;
+
+      old_block            = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+
+      // Update based on update type.
+      case (update_type)
+        // InitRound
+        INIT_UPDATE:
+          begin
+            old_block           = block;
+            addkey_block        = addroundkey(old_block, round_key);
+            inv_shiftrows_block = inv_shiftrows(addkey_block);
+            block_new           = inv_shiftrows_block;
+            block_w0_we         = 1;
+            block_w1_we         = 1;
+            block_w2_we         = 1;
+            block_w3_we         = 1;
+          end
+
+        SBOX_UPDATE:
+          begin
+            block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+            case (sword_ctr_reg)
+              2'h0:
+                begin
+                  tmp_sboxw   = block_w0_reg;
+                  block_w0_we = 1;
+                end
+
+              2'h1:
+                begin
+                  tmp_sboxw   = block_w1_reg;
+                  block_w1_we = 1;
+                end
+
+              2'h2:
+                begin
+                  tmp_sboxw   = block_w2_reg;
+                  block_w2_we = 1;
+                end
+
+              2'h3:
+                begin
+                  tmp_sboxw   = block_w3_reg;
+                  block_w3_we = 1;
+                end
+            endcase // case (sbox_mux_ctrl_reg)
+          end
+
+        MAIN_UPDATE:
+          begin
+            addkey_block         = addroundkey(old_block, round_key);
+            inv_mixcolumns_block = inv_mixcolumns(addkey_block);
+            inv_shiftrows_block  = inv_shiftrows(inv_mixcolumns_block);
+            block_new            = inv_shiftrows_block;
+            block_w0_we          = 1;
+            block_w1_we          = 1;
+            block_w2_we          = 1;
+            block_w3_we          = 1;
+          end
+
+        FINAL_UPDATE:
+          begin
+            block_new    = addroundkey(old_block, round_key);
+            block_w0_we  = 1;
+            block_w1_we  = 1;
+            block_w2_we  = 1;
+            block_w3_we  = 1;
+          end
+
+        default:
+          begin
+          end
+      endcase // case (update_type)
+    end // round_logic
+
+
+  //----------------------------------------------------------------
+  // sword_ctr
+  //
+  // The subbytes word counter with reset and increase logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : sword_ctr
+      sword_ctr_new = 2'h0;
+      sword_ctr_we  = 1'b0;
+
+      if (sword_ctr_rst)
+        begin
+          sword_ctr_new = 2'h0;
+          sword_ctr_we  = 1'b1;
+        end
+      else if (sword_ctr_inc)
+        begin
+          sword_ctr_new = sword_ctr_reg + 1'b1;
+          sword_ctr_we  = 1'b1;
+        end
+    end // sword_ctr
+
+
+  //----------------------------------------------------------------
+  // round_ctr
+  //
+  // The round counter with reset and increase logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_ctr
+      round_ctr_new = 4'h0;
+      round_ctr_we  = 1'b0;
+
+      if (round_ctr_set)
+        begin
+          if (keylen == AES_256_BIT_KEY)
+            begin
+              round_ctr_new = AES256_ROUNDS;
+            end
+          else
+            begin
+              round_ctr_new = AES128_ROUNDS;
+            end
+          round_ctr_we  = 1'b1;
+        end
+      else if (round_ctr_dec)
+        begin
+          round_ctr_new = round_ctr_reg - 1'b1;
+          round_ctr_we  = 1'b1;
+        end
+    end // round_ctr
+
+
+  //----------------------------------------------------------------
+  // decipher_ctrl
+  //
+  // The FSM that controls the decipher operations.
+  //----------------------------------------------------------------
+  always @*
+    begin: decipher_ctrl
+      sword_ctr_inc = 0;
+      sword_ctr_rst = 0;
+      round_ctr_dec = 0;
+      round_ctr_set = 0;
+      ready_new     = 0;
+      ready_we      = 0;
+      update_type   = NO_UPDATE;
+      dec_ctrl_new  = CTRL_IDLE;
+      dec_ctrl_we   = 0;
+
+      case(dec_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            if (next)
+              begin
+                round_ctr_set = 1;
+                ready_new     = 0;
+                ready_we      = 1;
+                dec_ctrl_new  = CTRL_INIT;
+                dec_ctrl_we   = 1;
+              end
+          end
+
+        CTRL_INIT:
+          begin
+            sword_ctr_rst = 1;
+            update_type   = INIT_UPDATE;
+            dec_ctrl_new  = CTRL_SBOX;
+            dec_ctrl_we   = 1;
+          end
+
+        CTRL_SBOX:
+          begin
+            sword_ctr_inc = 1;
+            update_type   = SBOX_UPDATE;
+            if (sword_ctr_reg == 2'h3)
+              begin
+                round_ctr_dec = 1;
+                dec_ctrl_new  = CTRL_MAIN;
+                dec_ctrl_we   = 1;
+              end
+          end
+
+        CTRL_MAIN:
+          begin
+            sword_ctr_rst = 1;
+            if (round_ctr_reg > 0)
+              begin
+                update_type   = MAIN_UPDATE;
+                dec_ctrl_new  = CTRL_SBOX;
+                dec_ctrl_we   = 1;
+              end
+            else
+              begin
+                update_type  = FINAL_UPDATE;
+                ready_new    = 1;
+                ready_we     = 1;
+                dec_ctrl_new = CTRL_IDLE;
+                dec_ctrl_we  = 1;
+              end
+          end
+
+        default:
+          begin
+            // Empty. Just here to make the synthesis tool happy.
+          end
+      endcase // case (dec_ctrl_reg)
+    end // decipher_ctrl
+
+endmodule // aes_decipher_block
+
+//======================================================================
+// EOF aes_decipher_block.v
+//======================================================================
diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v
new file mode 100644
index 0000000..2761d5b
--- /dev/null
+++ b/src/rtl/aes_encipher_block.v
@@ -0,0 +1,501 @@
+//======================================================================
+//
+// aes_encipher_block.v
+// --------------------
+// The AES encipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// enciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_encipher_block(
+                          input wire            clk,
+                          input wire            reset_n,
+
+                          input wire            next,
+
+                          input wire            keylen,
+                          output wire [3 : 0]   round,
+                          input wire [127 : 0]  round_key,
+
+                          output wire [31 : 0]  sboxw,
+                          input wire  [31 : 0]  new_sboxw,
+
+                          input wire [127 : 0]  block,
+                          output wire [127 : 0] new_block,
+                          output wire           ready
+                         );
+
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter AES_128_BIT_KEY = 1'h0;
+  parameter AES_256_BIT_KEY = 1'h1;
+
+  parameter AES128_ROUNDS = 4'ha;
+  parameter AES256_ROUNDS = 4'he;
+
+  parameter NO_UPDATE    = 3'h0;
+  parameter INIT_UPDATE  = 3'h1;
+  parameter SBOX_UPDATE  = 3'h2;
+  parameter MAIN_UPDATE  = 3'h3;
+  parameter FINAL_UPDATE = 3'h4;
+
+  parameter CTRL_IDLE  = 3'h0;
+  parameter CTRL_INIT  = 3'h1;
+  parameter CTRL_SBOX  = 3'h2;
+  parameter CTRL_MAIN  = 3'h3;
+  parameter CTRL_FINAL = 3'h4;
+
+
+  //----------------------------------------------------------------
+  // Round functions with sub functions.
+  //----------------------------------------------------------------
+  function [7 : 0] gm2(input [7 : 0] op);
+    begin
+      gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+    end
+  endfunction // gm2
+
+  function [7 : 0] gm3(input [7 : 0] op);
+    begin
+      gm3 = gm2(op) ^ op;
+    end
+  endfunction // gm3
+
+  function [31 : 0] mixw(input [31 : 0] w);
+    reg [7 : 0] b0, b1, b2, b3;
+    reg [7 : 0] mb0, mb1, mb2, mb3;
+    begin
+      b0 = w[31 : 24];
+      b1 = w[23 : 16];
+      b2 = w[15 : 08];
+      b3 = w[07 : 00];
+
+      mb0 = gm2(b0) ^ gm3(b1) ^ b2      ^ b3;
+      mb1 = b0      ^ gm2(b1) ^ gm3(b2) ^ b3;
+      mb2 = b0      ^ b1      ^ gm2(b2) ^ gm3(b3);
+      mb3 = gm3(b0) ^ b1      ^ b2      ^ gm2(b3);
+
+      mixw = {mb0, mb1, mb2, mb3};
+    end
+  endfunction // mixw
+
+  function [127 : 0] mixcolumns(input [127 : 0] data);
+    reg [31 : 0] w0, w1, w2, w3;
+    reg [31 : 0] ws0, ws1, ws2, ws3;
+    begin
+      w0 = data[127 : 096];
+      w1 = data[095 : 064];
+      w2 = data[063 : 032];
+      w3 = data[031 : 000];
+
+      ws0 = mixw(w0);
+      ws1 = mixw(w1);
+      ws2 = mixw(w2);
+      ws3 = mixw(w3);
+
+      mixcolumns = {ws0, ws1, ws2, ws3};
+    end
+  endfunction // mixcolumns
+
+  function [127 : 0] shiftrows(input [127 : 0] data);
+    reg [31 : 0] w0, w1, w2, w3;
+    reg [31 : 0] ws0, ws1, ws2, ws3;
+    begin
+      w0 = data[127 : 096];
+      w1 = data[095 : 064];
+      w2 = data[063 : 032];
+      w3 = data[031 : 000];
+
+      ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
+      ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
+      ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
+      ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
+
+      shiftrows = {ws0, ws1, ws2, ws3};
+    end
+  endfunction // shiftrows
+
+  function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+    begin
+      addroundkey = data ^ rkey;
+    end
+  endfunction // addroundkey
+
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
+  reg [1 : 0]   sword_ctr_reg;
+  reg [1 : 0]   sword_ctr_new;
+  reg           sword_ctr_we;
+  reg           sword_ctr_inc;
+  reg           sword_ctr_rst;
+
+  reg [3 : 0]   round_ctr_reg;
+  reg [3 : 0]   round_ctr_new;
+  reg           round_ctr_we;
+  reg           round_ctr_rst;
+  reg           round_ctr_inc;
+
+  reg [127 : 0] block_new;
+  reg [31 : 0]  block_w0_reg;
+  reg [31 : 0]  block_w1_reg;
+  reg [31 : 0]  block_w2_reg;
+  reg [31 : 0]  block_w3_reg;
+  reg           block_w0_we;
+  reg           block_w1_we;
+  reg           block_w2_we;
+  reg           block_w3_we;
+
+  reg           ready_reg;
+  reg           ready_new;
+  reg           ready_we;
+
+  reg [2 : 0]   enc_ctrl_reg;
+  reg [2 : 0]   enc_ctrl_new;
+  reg           enc_ctrl_we;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [2 : 0]  update_type;
+  reg [31 : 0] muxed_sboxw;
+
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
+  assign round     = round_ctr_reg;
+  assign sboxw     = muxed_sboxw;
+  assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+  assign ready     = ready_reg;
+
+
+  //----------------------------------------------------------------
+  // reg_update
+  //
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with asynchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk or negedge reset_n)
+    begin: reg_update
+      if (!reset_n)
+        begin
+          block_w0_reg  <= 32'h00000000;
+          block_w1_reg  <= 32'h00000000;
+          block_w2_reg  <= 32'h00000000;
+          block_w3_reg  <= 32'h00000000;
+          sword_ctr_reg <= 2'h0;
+          round_ctr_reg <= 4'h0;
+          ready_reg     <= 1;
+          enc_ctrl_reg  <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (block_w0_we)
+            begin
+              block_w0_reg <= block_new[127 : 096];
+            end
+
+          if (block_w1_we)
+            begin
+              block_w1_reg <= block_new[095 : 064];
+            end
+
+          if (block_w2_we)
+            begin
+              block_w2_reg <= block_new[063 : 032];
+            end
+
+          if (block_w3_we)
+            begin
+              block_w3_reg <= block_new[031 : 000];
+            end
+
+          if (sword_ctr_we)
+            begin
+              sword_ctr_reg <= sword_ctr_new;
+            end
+
+          if (round_ctr_we)
+            begin
+              round_ctr_reg <= round_ctr_new;
+            end
+
+          if (ready_we)
+            begin
+              ready_reg <= ready_new;
+            end
+
+          if (enc_ctrl_we)
+            begin
+              enc_ctrl_reg <= enc_ctrl_new;
+            end
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // round_logic
+  //
+  // The logic needed to implement init, main and final rounds.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_logic
+      reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
+      reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
+
+      block_new    = 128'h00000000000000000000000000000000;
+      muxed_sboxw  = 32'h00000000;
+      block_w0_we  = 0;
+      block_w1_we  = 0;
+      block_w2_we  = 0;
+      block_w3_we  = 0;
+
+      old_block          = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+      shiftrows_block    = shiftrows(old_block);
+      mixcolumns_block   = mixcolumns(shiftrows_block);
+      addkey_init_block  = addroundkey(block, round_key);
+      addkey_main_block  = addroundkey(mixcolumns_block, round_key);
+      addkey_final_block = addroundkey(shiftrows_block, round_key);
+
+      case (update_type)
+        INIT_UPDATE:
+          begin
+            block_new    = addkey_init_block;
+            block_w0_we  = 1;
+            block_w1_we  = 1;
+            block_w2_we  = 1;
+            block_w3_we  = 1;
+          end
+
+        SBOX_UPDATE:
+          begin
+            block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+            case (sword_ctr_reg)
+              2'h0:
+                begin
+                  muxed_sboxw = block_w0_reg;
+                  block_w0_we = 1;
+                end
+
+              2'h1:
+                begin
+                  muxed_sboxw = block_w1_reg;
+                  block_w1_we = 1;
+                end
+
+              2'h2:
+                begin
+                  muxed_sboxw = block_w2_reg;
+                  block_w2_we = 1;
+                end
+
+              2'h3:
+                begin
+                  muxed_sboxw = block_w3_reg;
+                  block_w3_we = 1;
+                end
+            endcase // case (sbox_mux_ctrl_reg)
+          end
+
+        MAIN_UPDATE:
+          begin
+            block_new    = addkey_main_block;
+            block_w0_we  = 1;
+            block_w1_we  = 1;
+            block_w2_we  = 1;
+            block_w3_we  = 1;
+          end
+
+        FINAL_UPDATE:
+          begin
+            block_new    = addkey_final_block;
+            block_w0_we  = 1;
+            block_w1_we  = 1;
+            block_w2_we  = 1;
+            block_w3_we  = 1;
+          end
+
+        default:
+          begin
+          end
+      endcase // case (update_type)
+    end // round_logic
+
+
+  //----------------------------------------------------------------
+  // sword_ctr
+  //
+  // The subbytes word counter with reset and increase logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : sword_ctr
+      sword_ctr_new = 2'h0;
+      sword_ctr_we  = 1'b0;
+
+      if (sword_ctr_rst)
+        begin
+          sword_ctr_new = 2'h0;
+          sword_ctr_we  = 1'b1;
+        end
+      else if (sword_ctr_inc)
+        begin
+          sword_ctr_new = sword_ctr_reg + 1'b1;
+          sword_ctr_we  = 1'b1;
+        end
+    end // sword_ctr
+
+
+  //----------------------------------------------------------------
+  // round_ctr
+  //
+  // The round counter with reset and increase logic.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_ctr
+      round_ctr_new = 4'h0;
+      round_ctr_we  = 1'b0;
+
+      if (round_ctr_rst)
+        begin
+          round_ctr_new = 4'h0;
+          round_ctr_we  = 1'b1;
+        end
+      else if (round_ctr_inc)
+        begin
+          round_ctr_new = round_ctr_reg + 1'b1;
+          round_ctr_we  = 1'b1;
+        end
+    end // round_ctr
+
+
+  //----------------------------------------------------------------
+  // encipher_ctrl
+  //
+  // The FSM that controls the encipher operations.
+  //----------------------------------------------------------------
+  always @*
+    begin: encipher_ctrl
+      reg [3 : 0]  num_rounds;
+
+      if (keylen == AES_256_BIT_KEY)
+        begin
+          num_rounds = AES256_ROUNDS;
+        end
+      else
+        begin
+          num_rounds = AES128_ROUNDS;
+        end
+
+      sword_ctr_inc = 0;
+      sword_ctr_rst = 0;
+      round_ctr_inc = 0;
+      round_ctr_rst = 0;
+      ready_new     = 0;
+      ready_we      = 0;
+      update_type   = NO_UPDATE;
+      enc_ctrl_new  = CTRL_IDLE;
+      enc_ctrl_we   = 0;
+
+      case(enc_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            if (next)
+              begin
+                round_ctr_rst = 1;
+                ready_new     = 0;
+                ready_we      = 1;
+                enc_ctrl_new  = CTRL_INIT;
+                enc_ctrl_we   = 1;
+              end
+          end
+
+        CTRL_INIT:
+          begin
+            round_ctr_inc = 1;
+            sword_ctr_rst = 1;
+            update_type   = INIT_UPDATE;
+            enc_ctrl_new  = CTRL_SBOX;
+            enc_ctrl_we   = 1;
+          end
+
+        CTRL_SBOX:
+          begin
+            sword_ctr_inc = 1;
+            update_type   = SBOX_UPDATE;
+            if (sword_ctr_reg == 2'h3)
+              begin
+                enc_ctrl_new  = CTRL_MAIN;
+                enc_ctrl_we   = 1;
+              end
+          end
+
+        CTRL_MAIN:
+          begin
+            sword_ctr_rst = 1;
+            round_ctr_inc = 1;
+            if (round_ctr_reg < num_rounds)
+              begin
+                update_type   = MAIN_UPDATE;
+                enc_ctrl_new  = CTRL_SBOX;
+                enc_ctrl_we   = 1;
+              end
+            else
+              begin
+                update_type  = FINAL_UPDATE;
+                ready_new    = 1;
+                ready_we     = 1;
+                enc_ctrl_new = CTRL_IDLE;
+                enc_ctrl_we  = 1;
+              end
+          end
+
+        default:
+          begin
+            // Empty. Just here to make the synthesis tool happy.
+          end
+      endcase // case (enc_ctrl_reg)
+    end // encipher_ctrl
+
+endmodule // aes_encipher_block
+
+//======================================================================
+// EOF aes_encipher_block.v
+//======================================================================
diff --git a/src/rtl/aes_inv_sbox.v b/src/rtl/aes_inv_sbox.v
new file mode 100644
index 0000000..6a3c01a
--- /dev/null
+++ b/src/rtl/aes_inv_sbox.v
@@ -0,0 +1,1136 @@
+//======================================================================
+//
+// aes_inv_sbox.v
+// --------------
+// The inverse AES S-box. Basically a 256 Byte ROM.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_inv_sbox(
+                    input wire  [31 : 0] sword,
+                    output wire [31 : 0] new_sword
+                   );
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [7 : 0] tmp_new_sbox0;
+  reg [7 : 0] tmp_new_sbox1;
+  reg [7 : 0] tmp_new_sbox2;
+  reg [7 : 0] tmp_new_sbox3;
+
+
+  //----------------------------------------------------------------
+  // Concurrent assignments for ports.
+  //----------------------------------------------------------------
+  assign new_sword = {tmp_new_sbox0, tmp_new_sbox1,
+                      tmp_new_sbox2, tmp_new_sbox3};
+
+
+  //----------------------------------------------------------------
+  // inv_sbox_rom0
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : inv_sbox_rom0
+      case(sword[31 : 24])
+        8'h00: tmp_new_sbox0 = 8'h52;
+	8'h01: tmp_new_sbox0 = 8'h09;
+	8'h02: tmp_new_sbox0 = 8'h6a;
+	8'h03: tmp_new_sbox0 = 8'hd5;
+	8'h04: tmp_new_sbox0 = 8'h30;
+	8'h05: tmp_new_sbox0 = 8'h36;
+	8'h06: tmp_new_sbox0 = 8'ha5;
+	8'h07: tmp_new_sbox0 = 8'h38;
+	8'h08: tmp_new_sbox0 = 8'hbf;
+	8'h09: tmp_new_sbox0 = 8'h40;
+	8'h0a: tmp_new_sbox0 = 8'ha3;
+	8'h0b: tmp_new_sbox0 = 8'h9e;
+	8'h0c: tmp_new_sbox0 = 8'h81;
+	8'h0d: tmp_new_sbox0 = 8'hf3;
+	8'h0e: tmp_new_sbox0 = 8'hd7;
+	8'h0f: tmp_new_sbox0 = 8'hfb;
+	8'h10: tmp_new_sbox0 = 8'h7c;
+	8'h11: tmp_new_sbox0 = 8'he3;
+	8'h12: tmp_new_sbox0 = 8'h39;
+	8'h13: tmp_new_sbox0 = 8'h82;
+	8'h14: tmp_new_sbox0 = 8'h9b;
+	8'h15: tmp_new_sbox0 = 8'h2f;
+	8'h16: tmp_new_sbox0 = 8'hff;
+	8'h17: tmp_new_sbox0 = 8'h87;
+	8'h18: tmp_new_sbox0 = 8'h34;
+	8'h19: tmp_new_sbox0 = 8'h8e;
+	8'h1a: tmp_new_sbox0 = 8'h43;
+	8'h1b: tmp_new_sbox0 = 8'h44;
+	8'h1c: tmp_new_sbox0 = 8'hc4;
+	8'h1d: tmp_new_sbox0 = 8'hde;
+	8'h1e: tmp_new_sbox0 = 8'he9;
+	8'h1f: tmp_new_sbox0 = 8'hcb;
+	8'h20: tmp_new_sbox0 = 8'h54;
+	8'h21: tmp_new_sbox0 = 8'h7b;
+	8'h22: tmp_new_sbox0 = 8'h94;
+	8'h23: tmp_new_sbox0 = 8'h32;
+	8'h24: tmp_new_sbox0 = 8'ha6;
+	8'h25: tmp_new_sbox0 = 8'hc2;
+	8'h26: tmp_new_sbox0 = 8'h23;
+	8'h27: tmp_new_sbox0 = 8'h3d;
+	8'h28: tmp_new_sbox0 = 8'hee;
+	8'h29: tmp_new_sbox0 = 8'h4c;
+	8'h2a: tmp_new_sbox0 = 8'h95;
+	8'h2b: tmp_new_sbox0 = 8'h0b;
+	8'h2c: tmp_new_sbox0 = 8'h42;
+	8'h2d: tmp_new_sbox0 = 8'hfa;
+	8'h2e: tmp_new_sbox0 = 8'hc3;
+	8'h2f: tmp_new_sbox0 = 8'h4e;
+	8'h30: tmp_new_sbox0 = 8'h08;
+	8'h31: tmp_new_sbox0 = 8'h2e;
+	8'h32: tmp_new_sbox0 = 8'ha1;
+	8'h33: tmp_new_sbox0 = 8'h66;
+	8'h34: tmp_new_sbox0 = 8'h28;
+	8'h35: tmp_new_sbox0 = 8'hd9;
+	8'h36: tmp_new_sbox0 = 8'h24;
+	8'h37: tmp_new_sbox0 = 8'hb2;
+	8'h38: tmp_new_sbox0 = 8'h76;
+	8'h39: tmp_new_sbox0 = 8'h5b;
+	8'h3a: tmp_new_sbox0 = 8'ha2;
+	8'h3b: tmp_new_sbox0 = 8'h49;
+	8'h3c: tmp_new_sbox0 = 8'h6d;
+	8'h3d: tmp_new_sbox0 = 8'h8b;
+	8'h3e: tmp_new_sbox0 = 8'hd1;
+	8'h3f: tmp_new_sbox0 = 8'h25;
+	8'h40: tmp_new_sbox0 = 8'h72;
+	8'h41: tmp_new_sbox0 = 8'hf8;
+	8'h42: tmp_new_sbox0 = 8'hf6;
+	8'h43: tmp_new_sbox0 = 8'h64;
+	8'h44: tmp_new_sbox0 = 8'h86;
+	8'h45: tmp_new_sbox0 = 8'h68;
+	8'h46: tmp_new_sbox0 = 8'h98;
+	8'h47: tmp_new_sbox0 = 8'h16;
+	8'h48: tmp_new_sbox0 = 8'hd4;
+	8'h49: tmp_new_sbox0 = 8'ha4;
+	8'h4a: tmp_new_sbox0 = 8'h5c;
+	8'h4b: tmp_new_sbox0 = 8'hcc;
+	8'h4c: tmp_new_sbox0 = 8'h5d;
+	8'h4d: tmp_new_sbox0 = 8'h65;
+	8'h4e: tmp_new_sbox0 = 8'hb6;
+	8'h4f: tmp_new_sbox0 = 8'h92;
+	8'h50: tmp_new_sbox0 = 8'h6c;
+	8'h51: tmp_new_sbox0 = 8'h70;
+	8'h52: tmp_new_sbox0 = 8'h48;
+	8'h53: tmp_new_sbox0 = 8'h50;
+	8'h54: tmp_new_sbox0 = 8'hfd;
+	8'h55: tmp_new_sbox0 = 8'hed;
+	8'h56: tmp_new_sbox0 = 8'hb9;
+	8'h57: tmp_new_sbox0 = 8'hda;
+	8'h58: tmp_new_sbox0 = 8'h5e;
+	8'h59: tmp_new_sbox0 = 8'h15;
+	8'h5a: tmp_new_sbox0 = 8'h46;
+	8'h5b: tmp_new_sbox0 = 8'h57;
+	8'h5c: tmp_new_sbox0 = 8'ha7;
+	8'h5d: tmp_new_sbox0 = 8'h8d;
+	8'h5e: tmp_new_sbox0 = 8'h9d;
+	8'h5f: tmp_new_sbox0 = 8'h84;
+	8'h60: tmp_new_sbox0 = 8'h90;
+	8'h61: tmp_new_sbox0 = 8'hd8;
+	8'h62: tmp_new_sbox0 = 8'hab;
+	8'h63: tmp_new_sbox0 = 8'h00;
+	8'h64: tmp_new_sbox0 = 8'h8c;
+	8'h65: tmp_new_sbox0 = 8'hbc;
+	8'h66: tmp_new_sbox0 = 8'hd3;
+	8'h67: tmp_new_sbox0 = 8'h0a;
+	8'h68: tmp_new_sbox0 = 8'hf7;
+	8'h69: tmp_new_sbox0 = 8'he4;
+	8'h6a: tmp_new_sbox0 = 8'h58;
+	8'h6b: tmp_new_sbox0 = 8'h05;
+	8'h6c: tmp_new_sbox0 = 8'hb8;
+	8'h6d: tmp_new_sbox0 = 8'hb3;
+	8'h6e: tmp_new_sbox0 = 8'h45;
+	8'h6f: tmp_new_sbox0 = 8'h06;
+	8'h70: tmp_new_sbox0 = 8'hd0;
+	8'h71: tmp_new_sbox0 = 8'h2c;
+	8'h72: tmp_new_sbox0 = 8'h1e;
+	8'h73: tmp_new_sbox0 = 8'h8f;
+	8'h74: tmp_new_sbox0 = 8'hca;
+	8'h75: tmp_new_sbox0 = 8'h3f;
+	8'h76: tmp_new_sbox0 = 8'h0f;
+	8'h77: tmp_new_sbox0 = 8'h02;
+	8'h78: tmp_new_sbox0 = 8'hc1;
+	8'h79: tmp_new_sbox0 = 8'haf;
+	8'h7a: tmp_new_sbox0 = 8'hbd;
+	8'h7b: tmp_new_sbox0 = 8'h03;
+	8'h7c: tmp_new_sbox0 = 8'h01;
+	8'h7d: tmp_new_sbox0 = 8'h13;
+	8'h7e: tmp_new_sbox0 = 8'h8a;
+	8'h7f: tmp_new_sbox0 = 8'h6b;
+	8'h80: tmp_new_sbox0 = 8'h3a;
+	8'h81: tmp_new_sbox0 = 8'h91;
+	8'h82: tmp_new_sbox0 = 8'h11;
+	8'h83: tmp_new_sbox0 = 8'h41;
+	8'h84: tmp_new_sbox0 = 8'h4f;
+	8'h85: tmp_new_sbox0 = 8'h67;
+	8'h86: tmp_new_sbox0 = 8'hdc;
+	8'h87: tmp_new_sbox0 = 8'hea;
+	8'h88: tmp_new_sbox0 = 8'h97;
+	8'h89: tmp_new_sbox0 = 8'hf2;
+	8'h8a: tmp_new_sbox0 = 8'hcf;
+	8'h8b: tmp_new_sbox0 = 8'hce;
+	8'h8c: tmp_new_sbox0 = 8'hf0;
+	8'h8d: tmp_new_sbox0 = 8'hb4;
+	8'h8e: tmp_new_sbox0 = 8'he6;
+	8'h8f: tmp_new_sbox0 = 8'h73;
+	8'h90: tmp_new_sbox0 = 8'h96;
+	8'h91: tmp_new_sbox0 = 8'hac;
+	8'h92: tmp_new_sbox0 = 8'h74;
+	8'h93: tmp_new_sbox0 = 8'h22;
+	8'h94: tmp_new_sbox0 = 8'he7;
+	8'h95: tmp_new_sbox0 = 8'had;
+	8'h96: tmp_new_sbox0 = 8'h35;
+	8'h97: tmp_new_sbox0 = 8'h85;
+	8'h98: tmp_new_sbox0 = 8'he2;
+	8'h99: tmp_new_sbox0 = 8'hf9;
+	8'h9a: tmp_new_sbox0 = 8'h37;
+	8'h9b: tmp_new_sbox0 = 8'he8;
+	8'h9c: tmp_new_sbox0 = 8'h1c;
+	8'h9d: tmp_new_sbox0 = 8'h75;
+	8'h9e: tmp_new_sbox0 = 8'hdf;
+	8'h9f: tmp_new_sbox0 = 8'h6e;
+	8'ha0: tmp_new_sbox0 = 8'h47;
+	8'ha1: tmp_new_sbox0 = 8'hf1;
+	8'ha2: tmp_new_sbox0 = 8'h1a;
+	8'ha3: tmp_new_sbox0 = 8'h71;
+	8'ha4: tmp_new_sbox0 = 8'h1d;
+	8'ha5: tmp_new_sbox0 = 8'h29;
+	8'ha6: tmp_new_sbox0 = 8'hc5;
+	8'ha7: tmp_new_sbox0 = 8'h89;
+	8'ha8: tmp_new_sbox0 = 8'h6f;
+	8'ha9: tmp_new_sbox0 = 8'hb7;
+	8'haa: tmp_new_sbox0 = 8'h62;
+	8'hab: tmp_new_sbox0 = 8'h0e;
+	8'hac: tmp_new_sbox0 = 8'haa;
+	8'had: tmp_new_sbox0 = 8'h18;
+	8'hae: tmp_new_sbox0 = 8'hbe;
+	8'haf: tmp_new_sbox0 = 8'h1b;
+	8'hb0: tmp_new_sbox0 = 8'hfc;
+	8'hb1: tmp_new_sbox0 = 8'h56;
+	8'hb2: tmp_new_sbox0 = 8'h3e;
+	8'hb3: tmp_new_sbox0 = 8'h4b;
+	8'hb4: tmp_new_sbox0 = 8'hc6;
+	8'hb5: tmp_new_sbox0 = 8'hd2;
+	8'hb6: tmp_new_sbox0 = 8'h79;
+	8'hb7: tmp_new_sbox0 = 8'h20;
+	8'hb8: tmp_new_sbox0 = 8'h9a;
+	8'hb9: tmp_new_sbox0 = 8'hdb;
+	8'hba: tmp_new_sbox0 = 8'hc0;
+	8'hbb: tmp_new_sbox0 = 8'hfe;
+	8'hbc: tmp_new_sbox0 = 8'h78;
+	8'hbd: tmp_new_sbox0 = 8'hcd;
+	8'hbe: tmp_new_sbox0 = 8'h5a;
+	8'hbf: tmp_new_sbox0 = 8'hf4;
+	8'hc0: tmp_new_sbox0 = 8'h1f;
+	8'hc1: tmp_new_sbox0 = 8'hdd;
+	8'hc2: tmp_new_sbox0 = 8'ha8;
+	8'hc3: tmp_new_sbox0 = 8'h33;
+	8'hc4: tmp_new_sbox0 = 8'h88;
+	8'hc5: tmp_new_sbox0 = 8'h07;
+	8'hc6: tmp_new_sbox0 = 8'hc7;
+	8'hc7: tmp_new_sbox0 = 8'h31;
+	8'hc8: tmp_new_sbox0 = 8'hb1;
+	8'hc9: tmp_new_sbox0 = 8'h12;
+	8'hca: tmp_new_sbox0 = 8'h10;
+	8'hcb: tmp_new_sbox0 = 8'h59;
+	8'hcc: tmp_new_sbox0 = 8'h27;
+	8'hcd: tmp_new_sbox0 = 8'h80;
+	8'hce: tmp_new_sbox0 = 8'hec;
+	8'hcf: tmp_new_sbox0 = 8'h5f;
+	8'hd0: tmp_new_sbox0 = 8'h60;
+	8'hd1: tmp_new_sbox0 = 8'h51;
+	8'hd2: tmp_new_sbox0 = 8'h7f;
+	8'hd3: tmp_new_sbox0 = 8'ha9;
+	8'hd4: tmp_new_sbox0 = 8'h19;
+	8'hd5: tmp_new_sbox0 = 8'hb5;
+	8'hd6: tmp_new_sbox0 = 8'h4a;
+	8'hd7: tmp_new_sbox0 = 8'h0d;
+	8'hd8: tmp_new_sbox0 = 8'h2d;
+	8'hd9: tmp_new_sbox0 = 8'he5;
+	8'hda: tmp_new_sbox0 = 8'h7a;
+	8'hdb: tmp_new_sbox0 = 8'h9f;
+	8'hdc: tmp_new_sbox0 = 8'h93;
+	8'hdd: tmp_new_sbox0 = 8'hc9;
+	8'hde: tmp_new_sbox0 = 8'h9c;
+	8'hdf: tmp_new_sbox0 = 8'hef;
+	8'he0: tmp_new_sbox0 = 8'ha0;
+	8'he1: tmp_new_sbox0 = 8'he0;
+	8'he2: tmp_new_sbox0 = 8'h3b;
+	8'he3: tmp_new_sbox0 = 8'h4d;
+	8'he4: tmp_new_sbox0 = 8'hae;
+	8'he5: tmp_new_sbox0 = 8'h2a;
+	8'he6: tmp_new_sbox0 = 8'hf5;
+	8'he7: tmp_new_sbox0 = 8'hb0;
+	8'he8: tmp_new_sbox0 = 8'hc8;
+	8'he9: tmp_new_sbox0 = 8'heb;
+	8'hea: tmp_new_sbox0 = 8'hbb;
+	8'heb: tmp_new_sbox0 = 8'h3c;
+	8'hec: tmp_new_sbox0 = 8'h83;
+	8'hed: tmp_new_sbox0 = 8'h53;
+	8'hee: tmp_new_sbox0 = 8'h99;
+	8'hef: tmp_new_sbox0 = 8'h61;
+	8'hf0: tmp_new_sbox0 = 8'h17;
+	8'hf1: tmp_new_sbox0 = 8'h2b;
+	8'hf2: tmp_new_sbox0 = 8'h04;
+	8'hf3: tmp_new_sbox0 = 8'h7e;
+	8'hf4: tmp_new_sbox0 = 8'hba;
+	8'hf5: tmp_new_sbox0 = 8'h77;
+	8'hf6: tmp_new_sbox0 = 8'hd6;
+	8'hf7: tmp_new_sbox0 = 8'h26;
+	8'hf8: tmp_new_sbox0 = 8'he1;
+	8'hf9: tmp_new_sbox0 = 8'h69;
+	8'hfa: tmp_new_sbox0 = 8'h14;
+	8'hfb: tmp_new_sbox0 = 8'h63;
+	8'hfc: tmp_new_sbox0 = 8'h55;
+	8'hfd: tmp_new_sbox0 = 8'h21;
+	8'hfe: tmp_new_sbox0 = 8'h0c;
+	8'hff: tmp_new_sbox0 = 8'h7d;
+      endcase // case (sword)
+    end // inv_sbox_rom0
+
+
+  //----------------------------------------------------------------
+  // inv_sbox_rom1
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : inv_sbox_rom1
+      case(sword[23 : 16])
+        8'h00: tmp_new_sbox1 = 8'h52;
+	8'h01: tmp_new_sbox1 = 8'h09;
+	8'h02: tmp_new_sbox1 = 8'h6a;
+	8'h03: tmp_new_sbox1 = 8'hd5;
+	8'h04: tmp_new_sbox1 = 8'h30;
+	8'h05: tmp_new_sbox1 = 8'h36;
+	8'h06: tmp_new_sbox1 = 8'ha5;
+	8'h07: tmp_new_sbox1 = 8'h38;
+	8'h08: tmp_new_sbox1 = 8'hbf;
+	8'h09: tmp_new_sbox1 = 8'h40;
+	8'h0a: tmp_new_sbox1 = 8'ha3;
+	8'h0b: tmp_new_sbox1 = 8'h9e;
+	8'h0c: tmp_new_sbox1 = 8'h81;
+	8'h0d: tmp_new_sbox1 = 8'hf3;
+	8'h0e: tmp_new_sbox1 = 8'hd7;
+	8'h0f: tmp_new_sbox1 = 8'hfb;
+	8'h10: tmp_new_sbox1 = 8'h7c;
+	8'h11: tmp_new_sbox1 = 8'he3;
+	8'h12: tmp_new_sbox1 = 8'h39;
+	8'h13: tmp_new_sbox1 = 8'h82;
+	8'h14: tmp_new_sbox1 = 8'h9b;
+	8'h15: tmp_new_sbox1 = 8'h2f;
+	8'h16: tmp_new_sbox1 = 8'hff;
+	8'h17: tmp_new_sbox1 = 8'h87;
+	8'h18: tmp_new_sbox1 = 8'h34;
+	8'h19: tmp_new_sbox1 = 8'h8e;
+	8'h1a: tmp_new_sbox1 = 8'h43;
+	8'h1b: tmp_new_sbox1 = 8'h44;
+	8'h1c: tmp_new_sbox1 = 8'hc4;
+	8'h1d: tmp_new_sbox1 = 8'hde;
+	8'h1e: tmp_new_sbox1 = 8'he9;
+	8'h1f: tmp_new_sbox1 = 8'hcb;
+	8'h20: tmp_new_sbox1 = 8'h54;
+	8'h21: tmp_new_sbox1 = 8'h7b;
+	8'h22: tmp_new_sbox1 = 8'h94;
+	8'h23: tmp_new_sbox1 = 8'h32;
+	8'h24: tmp_new_sbox1 = 8'ha6;
+	8'h25: tmp_new_sbox1 = 8'hc2;
+	8'h26: tmp_new_sbox1 = 8'h23;
+	8'h27: tmp_new_sbox1 = 8'h3d;
+	8'h28: tmp_new_sbox1 = 8'hee;
+	8'h29: tmp_new_sbox1 = 8'h4c;
+	8'h2a: tmp_new_sbox1 = 8'h95;
+	8'h2b: tmp_new_sbox1 = 8'h0b;
+	8'h2c: tmp_new_sbox1 = 8'h42;
+	8'h2d: tmp_new_sbox1 = 8'hfa;
+	8'h2e: tmp_new_sbox1 = 8'hc3;
+	8'h2f: tmp_new_sbox1 = 8'h4e;
+	8'h30: tmp_new_sbox1 = 8'h08;
+	8'h31: tmp_new_sbox1 = 8'h2e;
+	8'h32: tmp_new_sbox1 = 8'ha1;
+	8'h33: tmp_new_sbox1 = 8'h66;
+	8'h34: tmp_new_sbox1 = 8'h28;
+	8'h35: tmp_new_sbox1 = 8'hd9;
+	8'h36: tmp_new_sbox1 = 8'h24;
+	8'h37: tmp_new_sbox1 = 8'hb2;
+	8'h38: tmp_new_sbox1 = 8'h76;
+	8'h39: tmp_new_sbox1 = 8'h5b;
+	8'h3a: tmp_new_sbox1 = 8'ha2;
+	8'h3b: tmp_new_sbox1 = 8'h49;
+	8'h3c: tmp_new_sbox1 = 8'h6d;
+	8'h3d: tmp_new_sbox1 = 8'h8b;
+	8'h3e: tmp_new_sbox1 = 8'hd1;
+	8'h3f: tmp_new_sbox1 = 8'h25;
+	8'h40: tmp_new_sbox1 = 8'h72;
+	8'h41: tmp_new_sbox1 = 8'hf8;
+	8'h42: tmp_new_sbox1 = 8'hf6;
+	8'h43: tmp_new_sbox1 = 8'h64;
+	8'h44: tmp_new_sbox1 = 8'h86;
+	8'h45: tmp_new_sbox1 = 8'h68;
+	8'h46: tmp_new_sbox1 = 8'h98;
+	8'h47: tmp_new_sbox1 = 8'h16;
+	8'h48: tmp_new_sbox1 = 8'hd4;
+	8'h49: tmp_new_sbox1 = 8'ha4;
+	8'h4a: tmp_new_sbox1 = 8'h5c;
+	8'h4b: tmp_new_sbox1 = 8'hcc;
+	8'h4c: tmp_new_sbox1 = 8'h5d;
+	8'h4d: tmp_new_sbox1 = 8'h65;
+	8'h4e: tmp_new_sbox1 = 8'hb6;
+	8'h4f: tmp_new_sbox1 = 8'h92;
+	8'h50: tmp_new_sbox1 = 8'h6c;
+	8'h51: tmp_new_sbox1 = 8'h70;
+	8'h52: tmp_new_sbox1 = 8'h48;
+	8'h53: tmp_new_sbox1 = 8'h50;
+	8'h54: tmp_new_sbox1 = 8'hfd;
+	8'h55: tmp_new_sbox1 = 8'hed;
+	8'h56: tmp_new_sbox1 = 8'hb9;
+	8'h57: tmp_new_sbox1 = 8'hda;
+	8'h58: tmp_new_sbox1 = 8'h5e;
+	8'h59: tmp_new_sbox1 = 8'h15;
+	8'h5a: tmp_new_sbox1 = 8'h46;
+	8'h5b: tmp_new_sbox1 = 8'h57;
+	8'h5c: tmp_new_sbox1 = 8'ha7;
+	8'h5d: tmp_new_sbox1 = 8'h8d;
+	8'h5e: tmp_new_sbox1 = 8'h9d;
+	8'h5f: tmp_new_sbox1 = 8'h84;
+	8'h60: tmp_new_sbox1 = 8'h90;
+	8'h61: tmp_new_sbox1 = 8'hd8;
+	8'h62: tmp_new_sbox1 = 8'hab;
+	8'h63: tmp_new_sbox1 = 8'h00;
+	8'h64: tmp_new_sbox1 = 8'h8c;
+	8'h65: tmp_new_sbox1 = 8'hbc;
+	8'h66: tmp_new_sbox1 = 8'hd3;
+	8'h67: tmp_new_sbox1 = 8'h0a;
+	8'h68: tmp_new_sbox1 = 8'hf7;
+	8'h69: tmp_new_sbox1 = 8'he4;
+	8'h6a: tmp_new_sbox1 = 8'h58;
+	8'h6b: tmp_new_sbox1 = 8'h05;
+	8'h6c: tmp_new_sbox1 = 8'hb8;
+	8'h6d: tmp_new_sbox1 = 8'hb3;
+	8'h6e: tmp_new_sbox1 = 8'h45;
+	8'h6f: tmp_new_sbox1 = 8'h06;
+	8'h70: tmp_new_sbox1 = 8'hd0;
+	8'h71: tmp_new_sbox1 = 8'h2c;
+	8'h72: tmp_new_sbox1 = 8'h1e;
+	8'h73: tmp_new_sbox1 = 8'h8f;
+	8'h74: tmp_new_sbox1 = 8'hca;
+	8'h75: tmp_new_sbox1 = 8'h3f;
+	8'h76: tmp_new_sbox1 = 8'h0f;
+	8'h77: tmp_new_sbox1 = 8'h02;
+	8'h78: tmp_new_sbox1 = 8'hc1;
+	8'h79: tmp_new_sbox1 = 8'haf;
+	8'h7a: tmp_new_sbox1 = 8'hbd;
+	8'h7b: tmp_new_sbox1 = 8'h03;
+	8'h7c: tmp_new_sbox1 = 8'h01;
+	8'h7d: tmp_new_sbox1 = 8'h13;
+	8'h7e: tmp_new_sbox1 = 8'h8a;
+	8'h7f: tmp_new_sbox1 = 8'h6b;
+	8'h80: tmp_new_sbox1 = 8'h3a;
+	8'h81: tmp_new_sbox1 = 8'h91;
+	8'h82: tmp_new_sbox1 = 8'h11;
+	8'h83: tmp_new_sbox1 = 8'h41;
+	8'h84: tmp_new_sbox1 = 8'h4f;
+	8'h85: tmp_new_sbox1 = 8'h67;
+	8'h86: tmp_new_sbox1 = 8'hdc;
+	8'h87: tmp_new_sbox1 = 8'hea;
+	8'h88: tmp_new_sbox1 = 8'h97;
+	8'h89: tmp_new_sbox1 = 8'hf2;
+	8'h8a: tmp_new_sbox1 = 8'hcf;
+	8'h8b: tmp_new_sbox1 = 8'hce;
+	8'h8c: tmp_new_sbox1 = 8'hf0;
+	8'h8d: tmp_new_sbox1 = 8'hb4;
+	8'h8e: tmp_new_sbox1 = 8'he6;
+	8'h8f: tmp_new_sbox1 = 8'h73;
+	8'h90: tmp_new_sbox1 = 8'h96;
+	8'h91: tmp_new_sbox1 = 8'hac;
+	8'h92: tmp_new_sbox1 = 8'h74;
+	8'h93: tmp_new_sbox1 = 8'h22;
+	8'h94: tmp_new_sbox1 = 8'he7;
+	8'h95: tmp_new_sbox1 = 8'had;
+	8'h96: tmp_new_sbox1 = 8'h35;
+	8'h97: tmp_new_sbox1 = 8'h85;
+	8'h98: tmp_new_sbox1 = 8'he2;
+	8'h99: tmp_new_sbox1 = 8'hf9;
+	8'h9a: tmp_new_sbox1 = 8'h37;
+	8'h9b: tmp_new_sbox1 = 8'he8;
+	8'h9c: tmp_new_sbox1 = 8'h1c;
+	8'h9d: tmp_new_sbox1 = 8'h75;
+	8'h9e: tmp_new_sbox1 = 8'hdf;
+	8'h9f: tmp_new_sbox1 = 8'h6e;
+	8'ha0: tmp_new_sbox1 = 8'h47;
+	8'ha1: tmp_new_sbox1 = 8'hf1;
+	8'ha2: tmp_new_sbox1 = 8'h1a;
+	8'ha3: tmp_new_sbox1 = 8'h71;
+	8'ha4: tmp_new_sbox1 = 8'h1d;
+	8'ha5: tmp_new_sbox1 = 8'h29;
+	8'ha6: tmp_new_sbox1 = 8'hc5;
+	8'ha7: tmp_new_sbox1 = 8'h89;
+	8'ha8: tmp_new_sbox1 = 8'h6f;
+	8'ha9: tmp_new_sbox1 = 8'hb7;
+	8'haa: tmp_new_sbox1 = 8'h62;
+	8'hab: tmp_new_sbox1 = 8'h0e;
+	8'hac: tmp_new_sbox1 = 8'haa;
+	8'had: tmp_new_sbox1 = 8'h18;
+	8'hae: tmp_new_sbox1 = 8'hbe;
+	8'haf: tmp_new_sbox1 = 8'h1b;
+	8'hb0: tmp_new_sbox1 = 8'hfc;
+	8'hb1: tmp_new_sbox1 = 8'h56;
+	8'hb2: tmp_new_sbox1 = 8'h3e;
+	8'hb3: tmp_new_sbox1 = 8'h4b;
+	8'hb4: tmp_new_sbox1 = 8'hc6;
+	8'hb5: tmp_new_sbox1 = 8'hd2;
+	8'hb6: tmp_new_sbox1 = 8'h79;
+	8'hb7: tmp_new_sbox1 = 8'h20;
+	8'hb8: tmp_new_sbox1 = 8'h9a;
+	8'hb9: tmp_new_sbox1 = 8'hdb;
+	8'hba: tmp_new_sbox1 = 8'hc0;
+	8'hbb: tmp_new_sbox1 = 8'hfe;
+	8'hbc: tmp_new_sbox1 = 8'h78;
+	8'hbd: tmp_new_sbox1 = 8'hcd;
+	8'hbe: tmp_new_sbox1 = 8'h5a;
+	8'hbf: tmp_new_sbox1 = 8'hf4;
+	8'hc0: tmp_new_sbox1 = 8'h1f;
+	8'hc1: tmp_new_sbox1 = 8'hdd;
+	8'hc2: tmp_new_sbox1 = 8'ha8;
+	8'hc3: tmp_new_sbox1 = 8'h33;
+	8'hc4: tmp_new_sbox1 = 8'h88;
+	8'hc5: tmp_new_sbox1 = 8'h07;
+	8'hc6: tmp_new_sbox1 = 8'hc7;
+	8'hc7: tmp_new_sbox1 = 8'h31;
+	8'hc8: tmp_new_sbox1 = 8'hb1;
+	8'hc9: tmp_new_sbox1 = 8'h12;
+	8'hca: tmp_new_sbox1 = 8'h10;
+	8'hcb: tmp_new_sbox1 = 8'h59;
+	8'hcc: tmp_new_sbox1 = 8'h27;
+	8'hcd: tmp_new_sbox1 = 8'h80;
+	8'hce: tmp_new_sbox1 = 8'hec;
+	8'hcf: tmp_new_sbox1 = 8'h5f;
+	8'hd0: tmp_new_sbox1 = 8'h60;
+	8'hd1: tmp_new_sbox1 = 8'h51;
+	8'hd2: tmp_new_sbox1 = 8'h7f;
+	8'hd3: tmp_new_sbox1 = 8'ha9;
+	8'hd4: tmp_new_sbox1 = 8'h19;
+	8'hd5: tmp_new_sbox1 = 8'hb5;
+	8'hd6: tmp_new_sbox1 = 8'h4a;
+	8'hd7: tmp_new_sbox1 = 8'h0d;
+	8'hd8: tmp_new_sbox1 = 8'h2d;
+	8'hd9: tmp_new_sbox1 = 8'he5;
+	8'hda: tmp_new_sbox1 = 8'h7a;
+	8'hdb: tmp_new_sbox1 = 8'h9f;
+	8'hdc: tmp_new_sbox1 = 8'h93;
+	8'hdd: tmp_new_sbox1 = 8'hc9;
+	8'hde: tmp_new_sbox1 = 8'h9c;
+	8'hdf: tmp_new_sbox1 = 8'hef;
+	8'he0: tmp_new_sbox1 = 8'ha0;
+	8'he1: tmp_new_sbox1 = 8'he0;
+	8'he2: tmp_new_sbox1 = 8'h3b;
+	8'he3: tmp_new_sbox1 = 8'h4d;
+	8'he4: tmp_new_sbox1 = 8'hae;
+	8'he5: tmp_new_sbox1 = 8'h2a;
+	8'he6: tmp_new_sbox1 = 8'hf5;
+	8'he7: tmp_new_sbox1 = 8'hb0;
+	8'he8: tmp_new_sbox1 = 8'hc8;
+	8'he9: tmp_new_sbox1 = 8'heb;
+	8'hea: tmp_new_sbox1 = 8'hbb;
+	8'heb: tmp_new_sbox1 = 8'h3c;
+	8'hec: tmp_new_sbox1 = 8'h83;
+	8'hed: tmp_new_sbox1 = 8'h53;
+	8'hee: tmp_new_sbox1 = 8'h99;
+	8'hef: tmp_new_sbox1 = 8'h61;
+	8'hf0: tmp_new_sbox1 = 8'h17;
+	8'hf1: tmp_new_sbox1 = 8'h2b;
+	8'hf2: tmp_new_sbox1 = 8'h04;
+	8'hf3: tmp_new_sbox1 = 8'h7e;
+	8'hf4: tmp_new_sbox1 = 8'hba;
+	8'hf5: tmp_new_sbox1 = 8'h77;
+	8'hf6: tmp_new_sbox1 = 8'hd6;
+	8'hf7: tmp_new_sbox1 = 8'h26;
+	8'hf8: tmp_new_sbox1 = 8'he1;
+	8'hf9: tmp_new_sbox1 = 8'h69;
+	8'hfa: tmp_new_sbox1 = 8'h14;
+	8'hfb: tmp_new_sbox1 = 8'h63;
+	8'hfc: tmp_new_sbox1 = 8'h55;
+	8'hfd: tmp_new_sbox1 = 8'h21;
+	8'hfe: tmp_new_sbox1 = 8'h0c;
+	8'hff: tmp_new_sbox1 = 8'h7d;
+      endcase // case (sword)
+    end // inv_sbox_rom1
+
+
+  //----------------------------------------------------------------
+  // inv_sbox_rom2
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : inv_sbox_rom2
+      case(sword[15 : 8])
+        8'h00: tmp_new_sbox2 = 8'h52;
+	8'h01: tmp_new_sbox2 = 8'h09;
+	8'h02: tmp_new_sbox2 = 8'h6a;
+	8'h03: tmp_new_sbox2 = 8'hd5;
+	8'h04: tmp_new_sbox2 = 8'h30;
+	8'h05: tmp_new_sbox2 = 8'h36;
+	8'h06: tmp_new_sbox2 = 8'ha5;
+	8'h07: tmp_new_sbox2 = 8'h38;
+	8'h08: tmp_new_sbox2 = 8'hbf;
+	8'h09: tmp_new_sbox2 = 8'h40;
+	8'h0a: tmp_new_sbox2 = 8'ha3;
+	8'h0b: tmp_new_sbox2 = 8'h9e;
+	8'h0c: tmp_new_sbox2 = 8'h81;
+	8'h0d: tmp_new_sbox2 = 8'hf3;
+	8'h0e: tmp_new_sbox2 = 8'hd7;
+	8'h0f: tmp_new_sbox2 = 8'hfb;
+	8'h10: tmp_new_sbox2 = 8'h7c;
+	8'h11: tmp_new_sbox2 = 8'he3;
+	8'h12: tmp_new_sbox2 = 8'h39;
+	8'h13: tmp_new_sbox2 = 8'h82;
+	8'h14: tmp_new_sbox2 = 8'h9b;
+	8'h15: tmp_new_sbox2 = 8'h2f;
+	8'h16: tmp_new_sbox2 = 8'hff;
+	8'h17: tmp_new_sbox2 = 8'h87;
+	8'h18: tmp_new_sbox2 = 8'h34;
+	8'h19: tmp_new_sbox2 = 8'h8e;
+	8'h1a: tmp_new_sbox2 = 8'h43;
+	8'h1b: tmp_new_sbox2 = 8'h44;
+	8'h1c: tmp_new_sbox2 = 8'hc4;
+	8'h1d: tmp_new_sbox2 = 8'hde;
+	8'h1e: tmp_new_sbox2 = 8'he9;
+	8'h1f: tmp_new_sbox2 = 8'hcb;
+	8'h20: tmp_new_sbox2 = 8'h54;
+	8'h21: tmp_new_sbox2 = 8'h7b;
+	8'h22: tmp_new_sbox2 = 8'h94;
+	8'h23: tmp_new_sbox2 = 8'h32;
+	8'h24: tmp_new_sbox2 = 8'ha6;
+	8'h25: tmp_new_sbox2 = 8'hc2;
+	8'h26: tmp_new_sbox2 = 8'h23;
+	8'h27: tmp_new_sbox2 = 8'h3d;
+	8'h28: tmp_new_sbox2 = 8'hee;
+	8'h29: tmp_new_sbox2 = 8'h4c;
+	8'h2a: tmp_new_sbox2 = 8'h95;
+	8'h2b: tmp_new_sbox2 = 8'h0b;
+	8'h2c: tmp_new_sbox2 = 8'h42;
+	8'h2d: tmp_new_sbox2 = 8'hfa;
+	8'h2e: tmp_new_sbox2 = 8'hc3;
+	8'h2f: tmp_new_sbox2 = 8'h4e;
+	8'h30: tmp_new_sbox2 = 8'h08;
+	8'h31: tmp_new_sbox2 = 8'h2e;
+	8'h32: tmp_new_sbox2 = 8'ha1;
+	8'h33: tmp_new_sbox2 = 8'h66;
+	8'h34: tmp_new_sbox2 = 8'h28;
+	8'h35: tmp_new_sbox2 = 8'hd9;
+	8'h36: tmp_new_sbox2 = 8'h24;
+	8'h37: tmp_new_sbox2 = 8'hb2;
+	8'h38: tmp_new_sbox2 = 8'h76;
+	8'h39: tmp_new_sbox2 = 8'h5b;
+	8'h3a: tmp_new_sbox2 = 8'ha2;
+	8'h3b: tmp_new_sbox2 = 8'h49;
+	8'h3c: tmp_new_sbox2 = 8'h6d;
+	8'h3d: tmp_new_sbox2 = 8'h8b;
+	8'h3e: tmp_new_sbox2 = 8'hd1;
+	8'h3f: tmp_new_sbox2 = 8'h25;
+	8'h40: tmp_new_sbox2 = 8'h72;
+	8'h41: tmp_new_sbox2 = 8'hf8;
+	8'h42: tmp_new_sbox2 = 8'hf6;
+	8'h43: tmp_new_sbox2 = 8'h64;
+	8'h44: tmp_new_sbox2 = 8'h86;
+	8'h45: tmp_new_sbox2 = 8'h68;
+	8'h46: tmp_new_sbox2 = 8'h98;
+	8'h47: tmp_new_sbox2 = 8'h16;
+	8'h48: tmp_new_sbox2 = 8'hd4;
+	8'h49: tmp_new_sbox2 = 8'ha4;
+	8'h4a: tmp_new_sbox2 = 8'h5c;
+	8'h4b: tmp_new_sbox2 = 8'hcc;
+	8'h4c: tmp_new_sbox2 = 8'h5d;
+	8'h4d: tmp_new_sbox2 = 8'h65;
+	8'h4e: tmp_new_sbox2 = 8'hb6;
+	8'h4f: tmp_new_sbox2 = 8'h92;
+	8'h50: tmp_new_sbox2 = 8'h6c;
+	8'h51: tmp_new_sbox2 = 8'h70;
+	8'h52: tmp_new_sbox2 = 8'h48;
+	8'h53: tmp_new_sbox2 = 8'h50;
+	8'h54: tmp_new_sbox2 = 8'hfd;
+	8'h55: tmp_new_sbox2 = 8'hed;
+	8'h56: tmp_new_sbox2 = 8'hb9;
+	8'h57: tmp_new_sbox2 = 8'hda;
+	8'h58: tmp_new_sbox2 = 8'h5e;
+	8'h59: tmp_new_sbox2 = 8'h15;
+	8'h5a: tmp_new_sbox2 = 8'h46;
+	8'h5b: tmp_new_sbox2 = 8'h57;
+	8'h5c: tmp_new_sbox2 = 8'ha7;
+	8'h5d: tmp_new_sbox2 = 8'h8d;
+	8'h5e: tmp_new_sbox2 = 8'h9d;
+	8'h5f: tmp_new_sbox2 = 8'h84;
+	8'h60: tmp_new_sbox2 = 8'h90;
+	8'h61: tmp_new_sbox2 = 8'hd8;
+	8'h62: tmp_new_sbox2 = 8'hab;
+	8'h63: tmp_new_sbox2 = 8'h00;
+	8'h64: tmp_new_sbox2 = 8'h8c;
+	8'h65: tmp_new_sbox2 = 8'hbc;
+	8'h66: tmp_new_sbox2 = 8'hd3;
+	8'h67: tmp_new_sbox2 = 8'h0a;
+	8'h68: tmp_new_sbox2 = 8'hf7;
+	8'h69: tmp_new_sbox2 = 8'he4;
+	8'h6a: tmp_new_sbox2 = 8'h58;
+	8'h6b: tmp_new_sbox2 = 8'h05;
+	8'h6c: tmp_new_sbox2 = 8'hb8;
+	8'h6d: tmp_new_sbox2 = 8'hb3;
+	8'h6e: tmp_new_sbox2 = 8'h45;
+	8'h6f: tmp_new_sbox2 = 8'h06;
+	8'h70: tmp_new_sbox2 = 8'hd0;
+	8'h71: tmp_new_sbox2 = 8'h2c;
+	8'h72: tmp_new_sbox2 = 8'h1e;
+	8'h73: tmp_new_sbox2 = 8'h8f;
+	8'h74: tmp_new_sbox2 = 8'hca;
+	8'h75: tmp_new_sbox2 = 8'h3f;
+	8'h76: tmp_new_sbox2 = 8'h0f;
+	8'h77: tmp_new_sbox2 = 8'h02;
+	8'h78: tmp_new_sbox2 = 8'hc1;
+	8'h79: tmp_new_sbox2 = 8'haf;
+	8'h7a: tmp_new_sbox2 = 8'hbd;
+	8'h7b: tmp_new_sbox2 = 8'h03;
+	8'h7c: tmp_new_sbox2 = 8'h01;
+	8'h7d: tmp_new_sbox2 = 8'h13;
+	8'h7e: tmp_new_sbox2 = 8'h8a;
+	8'h7f: tmp_new_sbox2 = 8'h6b;
+	8'h80: tmp_new_sbox2 = 8'h3a;
+	8'h81: tmp_new_sbox2 = 8'h91;
+	8'h82: tmp_new_sbox2 = 8'h11;
+	8'h83: tmp_new_sbox2 = 8'h41;
+	8'h84: tmp_new_sbox2 = 8'h4f;
+	8'h85: tmp_new_sbox2 = 8'h67;
+	8'h86: tmp_new_sbox2 = 8'hdc;
+	8'h87: tmp_new_sbox2 = 8'hea;
+	8'h88: tmp_new_sbox2 = 8'h97;
+	8'h89: tmp_new_sbox2 = 8'hf2;
+	8'h8a: tmp_new_sbox2 = 8'hcf;
+	8'h8b: tmp_new_sbox2 = 8'hce;
+	8'h8c: tmp_new_sbox2 = 8'hf0;
+	8'h8d: tmp_new_sbox2 = 8'hb4;
+	8'h8e: tmp_new_sbox2 = 8'he6;
+	8'h8f: tmp_new_sbox2 = 8'h73;
+	8'h90: tmp_new_sbox2 = 8'h96;
+	8'h91: tmp_new_sbox2 = 8'hac;
+	8'h92: tmp_new_sbox2 = 8'h74;
+	8'h93: tmp_new_sbox2 = 8'h22;
+	8'h94: tmp_new_sbox2 = 8'he7;
+	8'h95: tmp_new_sbox2 = 8'had;
+	8'h96: tmp_new_sbox2 = 8'h35;
+	8'h97: tmp_new_sbox2 = 8'h85;
+	8'h98: tmp_new_sbox2 = 8'he2;
+	8'h99: tmp_new_sbox2 = 8'hf9;
+	8'h9a: tmp_new_sbox2 = 8'h37;
+	8'h9b: tmp_new_sbox2 = 8'he8;
+	8'h9c: tmp_new_sbox2 = 8'h1c;
+	8'h9d: tmp_new_sbox2 = 8'h75;
+	8'h9e: tmp_new_sbox2 = 8'hdf;
+	8'h9f: tmp_new_sbox2 = 8'h6e;
+	8'ha0: tmp_new_sbox2 = 8'h47;
+	8'ha1: tmp_new_sbox2 = 8'hf1;
+	8'ha2: tmp_new_sbox2 = 8'h1a;
+	8'ha3: tmp_new_sbox2 = 8'h71;
+	8'ha4: tmp_new_sbox2 = 8'h1d;
+	8'ha5: tmp_new_sbox2 = 8'h29;
+	8'ha6: tmp_new_sbox2 = 8'hc5;
+	8'ha7: tmp_new_sbox2 = 8'h89;
+	8'ha8: tmp_new_sbox2 = 8'h6f;
+	8'ha9: tmp_new_sbox2 = 8'hb7;
+	8'haa: tmp_new_sbox2 = 8'h62;
+	8'hab: tmp_new_sbox2 = 8'h0e;
+	8'hac: tmp_new_sbox2 = 8'haa;
+	8'had: tmp_new_sbox2 = 8'h18;
+	8'hae: tmp_new_sbox2 = 8'hbe;
+	8'haf: tmp_new_sbox2 = 8'h1b;
+	8'hb0: tmp_new_sbox2 = 8'hfc;
+	8'hb1: tmp_new_sbox2 = 8'h56;
+	8'hb2: tmp_new_sbox2 = 8'h3e;
+	8'hb3: tmp_new_sbox2 = 8'h4b;
+	8'hb4: tmp_new_sbox2 = 8'hc6;
+	8'hb5: tmp_new_sbox2 = 8'hd2;
+	8'hb6: tmp_new_sbox2 = 8'h79;
+	8'hb7: tmp_new_sbox2 = 8'h20;
+	8'hb8: tmp_new_sbox2 = 8'h9a;
+	8'hb9: tmp_new_sbox2 = 8'hdb;
+	8'hba: tmp_new_sbox2 = 8'hc0;
+	8'hbb: tmp_new_sbox2 = 8'hfe;
+	8'hbc: tmp_new_sbox2 = 8'h78;
+	8'hbd: tmp_new_sbox2 = 8'hcd;
+	8'hbe: tmp_new_sbox2 = 8'h5a;
+	8'hbf: tmp_new_sbox2 = 8'hf4;
+	8'hc0: tmp_new_sbox2 = 8'h1f;
+	8'hc1: tmp_new_sbox2 = 8'hdd;
+	8'hc2: tmp_new_sbox2 = 8'ha8;
+	8'hc3: tmp_new_sbox2 = 8'h33;
+	8'hc4: tmp_new_sbox2 = 8'h88;
+	8'hc5: tmp_new_sbox2 = 8'h07;
+	8'hc6: tmp_new_sbox2 = 8'hc7;
+	8'hc7: tmp_new_sbox2 = 8'h31;
+	8'hc8: tmp_new_sbox2 = 8'hb1;
+	8'hc9: tmp_new_sbox2 = 8'h12;
+	8'hca: tmp_new_sbox2 = 8'h10;
+	8'hcb: tmp_new_sbox2 = 8'h59;
+	8'hcc: tmp_new_sbox2 = 8'h27;
+	8'hcd: tmp_new_sbox2 = 8'h80;
+	8'hce: tmp_new_sbox2 = 8'hec;
+	8'hcf: tmp_new_sbox2 = 8'h5f;
+	8'hd0: tmp_new_sbox2 = 8'h60;
+	8'hd1: tmp_new_sbox2 = 8'h51;
+	8'hd2: tmp_new_sbox2 = 8'h7f;
+	8'hd3: tmp_new_sbox2 = 8'ha9;
+	8'hd4: tmp_new_sbox2 = 8'h19;
+	8'hd5: tmp_new_sbox2 = 8'hb5;
+	8'hd6: tmp_new_sbox2 = 8'h4a;
+	8'hd7: tmp_new_sbox2 = 8'h0d;
+	8'hd8: tmp_new_sbox2 = 8'h2d;
+	8'hd9: tmp_new_sbox2 = 8'he5;
+	8'hda: tmp_new_sbox2 = 8'h7a;
+	8'hdb: tmp_new_sbox2 = 8'h9f;
+	8'hdc: tmp_new_sbox2 = 8'h93;
+	8'hdd: tmp_new_sbox2 = 8'hc9;
+	8'hde: tmp_new_sbox2 = 8'h9c;
+	8'hdf: tmp_new_sbox2 = 8'hef;
+	8'he0: tmp_new_sbox2 = 8'ha0;
+	8'he1: tmp_new_sbox2 = 8'he0;
+	8'he2: tmp_new_sbox2 = 8'h3b;
+	8'he3: tmp_new_sbox2 = 8'h4d;
+	8'he4: tmp_new_sbox2 = 8'hae;
+	8'he5: tmp_new_sbox2 = 8'h2a;
+	8'he6: tmp_new_sbox2 = 8'hf5;
+	8'he7: tmp_new_sbox2 = 8'hb0;
+	8'he8: tmp_new_sbox2 = 8'hc8;
+	8'he9: tmp_new_sbox2 = 8'heb;
+	8'hea: tmp_new_sbox2 = 8'hbb;
+	8'heb: tmp_new_sbox2 = 8'h3c;
+	8'hec: tmp_new_sbox2 = 8'h83;
+	8'hed: tmp_new_sbox2 = 8'h53;
+	8'hee: tmp_new_sbox2 = 8'h99;
+	8'hef: tmp_new_sbox2 = 8'h61;
+	8'hf0: tmp_new_sbox2 = 8'h17;
+	8'hf1: tmp_new_sbox2 = 8'h2b;
+	8'hf2: tmp_new_sbox2 = 8'h04;
+	8'hf3: tmp_new_sbox2 = 8'h7e;
+	8'hf4: tmp_new_sbox2 = 8'hba;
+	8'hf5: tmp_new_sbox2 = 8'h77;
+	8'hf6: tmp_new_sbox2 = 8'hd6;
+	8'hf7: tmp_new_sbox2 = 8'h26;
+	8'hf8: tmp_new_sbox2 = 8'he1;
+	8'hf9: tmp_new_sbox2 = 8'h69;
+	8'hfa: tmp_new_sbox2 = 8'h14;
+	8'hfb: tmp_new_sbox2 = 8'h63;
+	8'hfc: tmp_new_sbox2 = 8'h55;
+	8'hfd: tmp_new_sbox2 = 8'h21;
+	8'hfe: tmp_new_sbox2 = 8'h0c;
+	8'hff: tmp_new_sbox2 = 8'h7d;
+      endcase // case (sword)
+    end // inv_sbox_rom2
+
+
+  //----------------------------------------------------------------
+  // inv_sbox_rom3
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : inv_sbox_rom3
+      case(sword[7 : 0])
+        8'h00: tmp_new_sbox3 = 8'h52;
+	8'h01: tmp_new_sbox3 = 8'h09;
+	8'h02: tmp_new_sbox3 = 8'h6a;
+	8'h03: tmp_new_sbox3 = 8'hd5;
+	8'h04: tmp_new_sbox3 = 8'h30;
+	8'h05: tmp_new_sbox3 = 8'h36;
+	8'h06: tmp_new_sbox3 = 8'ha5;
+	8'h07: tmp_new_sbox3 = 8'h38;
+	8'h08: tmp_new_sbox3 = 8'hbf;
+	8'h09: tmp_new_sbox3 = 8'h40;
+	8'h0a: tmp_new_sbox3 = 8'ha3;
+	8'h0b: tmp_new_sbox3 = 8'h9e;
+	8'h0c: tmp_new_sbox3 = 8'h81;
+	8'h0d: tmp_new_sbox3 = 8'hf3;
+	8'h0e: tmp_new_sbox3 = 8'hd7;
+	8'h0f: tmp_new_sbox3 = 8'hfb;
+	8'h10: tmp_new_sbox3 = 8'h7c;
+	8'h11: tmp_new_sbox3 = 8'he3;
+	8'h12: tmp_new_sbox3 = 8'h39;
+	8'h13: tmp_new_sbox3 = 8'h82;
+	8'h14: tmp_new_sbox3 = 8'h9b;
+	8'h15: tmp_new_sbox3 = 8'h2f;
+	8'h16: tmp_new_sbox3 = 8'hff;
+	8'h17: tmp_new_sbox3 = 8'h87;
+	8'h18: tmp_new_sbox3 = 8'h34;
+	8'h19: tmp_new_sbox3 = 8'h8e;
+	8'h1a: tmp_new_sbox3 = 8'h43;
+	8'h1b: tmp_new_sbox3 = 8'h44;
+	8'h1c: tmp_new_sbox3 = 8'hc4;
+	8'h1d: tmp_new_sbox3 = 8'hde;
+	8'h1e: tmp_new_sbox3 = 8'he9;
+	8'h1f: tmp_new_sbox3 = 8'hcb;
+	8'h20: tmp_new_sbox3 = 8'h54;
+	8'h21: tmp_new_sbox3 = 8'h7b;
+	8'h22: tmp_new_sbox3 = 8'h94;
+	8'h23: tmp_new_sbox3 = 8'h32;
+	8'h24: tmp_new_sbox3 = 8'ha6;
+	8'h25: tmp_new_sbox3 = 8'hc2;
+	8'h26: tmp_new_sbox3 = 8'h23;
+	8'h27: tmp_new_sbox3 = 8'h3d;
+	8'h28: tmp_new_sbox3 = 8'hee;
+	8'h29: tmp_new_sbox3 = 8'h4c;
+	8'h2a: tmp_new_sbox3 = 8'h95;
+	8'h2b: tmp_new_sbox3 = 8'h0b;
+	8'h2c: tmp_new_sbox3 = 8'h42;
+	8'h2d: tmp_new_sbox3 = 8'hfa;
+	8'h2e: tmp_new_sbox3 = 8'hc3;
+	8'h2f: tmp_new_sbox3 = 8'h4e;
+	8'h30: tmp_new_sbox3 = 8'h08;
+	8'h31: tmp_new_sbox3 = 8'h2e;
+	8'h32: tmp_new_sbox3 = 8'ha1;
+	8'h33: tmp_new_sbox3 = 8'h66;
+	8'h34: tmp_new_sbox3 = 8'h28;
+	8'h35: tmp_new_sbox3 = 8'hd9;
+	8'h36: tmp_new_sbox3 = 8'h24;
+	8'h37: tmp_new_sbox3 = 8'hb2;
+	8'h38: tmp_new_sbox3 = 8'h76;
+	8'h39: tmp_new_sbox3 = 8'h5b;
+	8'h3a: tmp_new_sbox3 = 8'ha2;
+	8'h3b: tmp_new_sbox3 = 8'h49;
+	8'h3c: tmp_new_sbox3 = 8'h6d;
+	8'h3d: tmp_new_sbox3 = 8'h8b;
+	8'h3e: tmp_new_sbox3 = 8'hd1;
+	8'h3f: tmp_new_sbox3 = 8'h25;
+	8'h40: tmp_new_sbox3 = 8'h72;
+	8'h41: tmp_new_sbox3 = 8'hf8;
+	8'h42: tmp_new_sbox3 = 8'hf6;
+	8'h43: tmp_new_sbox3 = 8'h64;
+	8'h44: tmp_new_sbox3 = 8'h86;
+	8'h45: tmp_new_sbox3 = 8'h68;
+	8'h46: tmp_new_sbox3 = 8'h98;
+	8'h47: tmp_new_sbox3 = 8'h16;
+	8'h48: tmp_new_sbox3 = 8'hd4;
+	8'h49: tmp_new_sbox3 = 8'ha4;
+	8'h4a: tmp_new_sbox3 = 8'h5c;
+	8'h4b: tmp_new_sbox3 = 8'hcc;
+	8'h4c: tmp_new_sbox3 = 8'h5d;
+	8'h4d: tmp_new_sbox3 = 8'h65;
+	8'h4e: tmp_new_sbox3 = 8'hb6;
+	8'h4f: tmp_new_sbox3 = 8'h92;
+	8'h50: tmp_new_sbox3 = 8'h6c;
+	8'h51: tmp_new_sbox3 = 8'h70;
+	8'h52: tmp_new_sbox3 = 8'h48;
+	8'h53: tmp_new_sbox3 = 8'h50;
+	8'h54: tmp_new_sbox3 = 8'hfd;
+	8'h55: tmp_new_sbox3 = 8'hed;
+	8'h56: tmp_new_sbox3 = 8'hb9;
+	8'h57: tmp_new_sbox3 = 8'hda;
+	8'h58: tmp_new_sbox3 = 8'h5e;
+	8'h59: tmp_new_sbox3 = 8'h15;
+	8'h5a: tmp_new_sbox3 = 8'h46;
+	8'h5b: tmp_new_sbox3 = 8'h57;
+	8'h5c: tmp_new_sbox3 = 8'ha7;
+	8'h5d: tmp_new_sbox3 = 8'h8d;
+	8'h5e: tmp_new_sbox3 = 8'h9d;
+	8'h5f: tmp_new_sbox3 = 8'h84;
+	8'h60: tmp_new_sbox3 = 8'h90;
+	8'h61: tmp_new_sbox3 = 8'hd8;
+	8'h62: tmp_new_sbox3 = 8'hab;
+	8'h63: tmp_new_sbox3 = 8'h00;
+	8'h64: tmp_new_sbox3 = 8'h8c;
+	8'h65: tmp_new_sbox3 = 8'hbc;
+	8'h66: tmp_new_sbox3 = 8'hd3;
+	8'h67: tmp_new_sbox3 = 8'h0a;
+	8'h68: tmp_new_sbox3 = 8'hf7;
+	8'h69: tmp_new_sbox3 = 8'he4;
+	8'h6a: tmp_new_sbox3 = 8'h58;
+	8'h6b: tmp_new_sbox3 = 8'h05;
+	8'h6c: tmp_new_sbox3 = 8'hb8;
+	8'h6d: tmp_new_sbox3 = 8'hb3;
+	8'h6e: tmp_new_sbox3 = 8'h45;
+	8'h6f: tmp_new_sbox3 = 8'h06;
+	8'h70: tmp_new_sbox3 = 8'hd0;
+	8'h71: tmp_new_sbox3 = 8'h2c;
+	8'h72: tmp_new_sbox3 = 8'h1e;
+	8'h73: tmp_new_sbox3 = 8'h8f;
+	8'h74: tmp_new_sbox3 = 8'hca;
+	8'h75: tmp_new_sbox3 = 8'h3f;
+	8'h76: tmp_new_sbox3 = 8'h0f;
+	8'h77: tmp_new_sbox3 = 8'h02;
+	8'h78: tmp_new_sbox3 = 8'hc1;
+	8'h79: tmp_new_sbox3 = 8'haf;
+	8'h7a: tmp_new_sbox3 = 8'hbd;
+	8'h7b: tmp_new_sbox3 = 8'h03;
+	8'h7c: tmp_new_sbox3 = 8'h01;
+	8'h7d: tmp_new_sbox3 = 8'h13;
+	8'h7e: tmp_new_sbox3 = 8'h8a;
+	8'h7f: tmp_new_sbox3 = 8'h6b;
+	8'h80: tmp_new_sbox3 = 8'h3a;
+	8'h81: tmp_new_sbox3 = 8'h91;
+	8'h82: tmp_new_sbox3 = 8'h11;
+	8'h83: tmp_new_sbox3 = 8'h41;
+	8'h84: tmp_new_sbox3 = 8'h4f;
+	8'h85: tmp_new_sbox3 = 8'h67;
+	8'h86: tmp_new_sbox3 = 8'hdc;
+	8'h87: tmp_new_sbox3 = 8'hea;
+	8'h88: tmp_new_sbox3 = 8'h97;
+	8'h89: tmp_new_sbox3 = 8'hf2;
+	8'h8a: tmp_new_sbox3 = 8'hcf;
+	8'h8b: tmp_new_sbox3 = 8'hce;
+	8'h8c: tmp_new_sbox3 = 8'hf0;
+	8'h8d: tmp_new_sbox3 = 8'hb4;
+	8'h8e: tmp_new_sbox3 = 8'he6;
+	8'h8f: tmp_new_sbox3 = 8'h73;
+	8'h90: tmp_new_sbox3 = 8'h96;
+	8'h91: tmp_new_sbox3 = 8'hac;
+	8'h92: tmp_new_sbox3 = 8'h74;
+	8'h93: tmp_new_sbox3 = 8'h22;
+	8'h94: tmp_new_sbox3 = 8'he7;
+	8'h95: tmp_new_sbox3 = 8'had;
+	8'h96: tmp_new_sbox3 = 8'h35;
+	8'h97: tmp_new_sbox3 = 8'h85;
+	8'h98: tmp_new_sbox3 = 8'he2;
+	8'h99: tmp_new_sbox3 = 8'hf9;
+	8'h9a: tmp_new_sbox3 = 8'h37;
+	8'h9b: tmp_new_sbox3 = 8'he8;
+	8'h9c: tmp_new_sbox3 = 8'h1c;
+	8'h9d: tmp_new_sbox3 = 8'h75;
+	8'h9e: tmp_new_sbox3 = 8'hdf;
+	8'h9f: tmp_new_sbox3 = 8'h6e;
+	8'ha0: tmp_new_sbox3 = 8'h47;
+	8'ha1: tmp_new_sbox3 = 8'hf1;
+	8'ha2: tmp_new_sbox3 = 8'h1a;
+	8'ha3: tmp_new_sbox3 = 8'h71;
+	8'ha4: tmp_new_sbox3 = 8'h1d;
+	8'ha5: tmp_new_sbox3 = 8'h29;
+	8'ha6: tmp_new_sbox3 = 8'hc5;
+	8'ha7: tmp_new_sbox3 = 8'h89;
+	8'ha8: tmp_new_sbox3 = 8'h6f;
+	8'ha9: tmp_new_sbox3 = 8'hb7;
+	8'haa: tmp_new_sbox3 = 8'h62;
+	8'hab: tmp_new_sbox3 = 8'h0e;
+	8'hac: tmp_new_sbox3 = 8'haa;
+	8'had: tmp_new_sbox3 = 8'h18;
+	8'hae: tmp_new_sbox3 = 8'hbe;
+	8'haf: tmp_new_sbox3 = 8'h1b;
+	8'hb0: tmp_new_sbox3 = 8'hfc;
+	8'hb1: tmp_new_sbox3 = 8'h56;
+	8'hb2: tmp_new_sbox3 = 8'h3e;
+	8'hb3: tmp_new_sbox3 = 8'h4b;
+	8'hb4: tmp_new_sbox3 = 8'hc6;
+	8'hb5: tmp_new_sbox3 = 8'hd2;
+	8'hb6: tmp_new_sbox3 = 8'h79;
+	8'hb7: tmp_new_sbox3 = 8'h20;
+	8'hb8: tmp_new_sbox3 = 8'h9a;
+	8'hb9: tmp_new_sbox3 = 8'hdb;
+	8'hba: tmp_new_sbox3 = 8'hc0;
+	8'hbb: tmp_new_sbox3 = 8'hfe;
+	8'hbc: tmp_new_sbox3 = 8'h78;
+	8'hbd: tmp_new_sbox3 = 8'hcd;
+	8'hbe: tmp_new_sbox3 = 8'h5a;
+	8'hbf: tmp_new_sbox3 = 8'hf4;
+	8'hc0: tmp_new_sbox3 = 8'h1f;
+	8'hc1: tmp_new_sbox3 = 8'hdd;
+	8'hc2: tmp_new_sbox3 = 8'ha8;
+	8'hc3: tmp_new_sbox3 = 8'h33;
+	8'hc4: tmp_new_sbox3 = 8'h88;
+	8'hc5: tmp_new_sbox3 = 8'h07;
+	8'hc6: tmp_new_sbox3 = 8'hc7;
+	8'hc7: tmp_new_sbox3 = 8'h31;
+	8'hc8: tmp_new_sbox3 = 8'hb1;
+	8'hc9: tmp_new_sbox3 = 8'h12;
+	8'hca: tmp_new_sbox3 = 8'h10;
+	8'hcb: tmp_new_sbox3 = 8'h59;
+	8'hcc: tmp_new_sbox3 = 8'h27;
+	8'hcd: tmp_new_sbox3 = 8'h80;
+	8'hce: tmp_new_sbox3 = 8'hec;
+	8'hcf: tmp_new_sbox3 = 8'h5f;
+	8'hd0: tmp_new_sbox3 = 8'h60;
+	8'hd1: tmp_new_sbox3 = 8'h51;
+	8'hd2: tmp_new_sbox3 = 8'h7f;
+	8'hd3: tmp_new_sbox3 = 8'ha9;
+	8'hd4: tmp_new_sbox3 = 8'h19;
+	8'hd5: tmp_new_sbox3 = 8'hb5;
+	8'hd6: tmp_new_sbox3 = 8'h4a;
+	8'hd7: tmp_new_sbox3 = 8'h0d;
+	8'hd8: tmp_new_sbox3 = 8'h2d;
+	8'hd9: tmp_new_sbox3 = 8'he5;
+	8'hda: tmp_new_sbox3 = 8'h7a;
+	8'hdb: tmp_new_sbox3 = 8'h9f;
+	8'hdc: tmp_new_sbox3 = 8'h93;
+	8'hdd: tmp_new_sbox3 = 8'hc9;
+	8'hde: tmp_new_sbox3 = 8'h9c;
+	8'hdf: tmp_new_sbox3 = 8'hef;
+	8'he0: tmp_new_sbox3 = 8'ha0;
+	8'he1: tmp_new_sbox3 = 8'he0;
+	8'he2: tmp_new_sbox3 = 8'h3b;
+	8'he3: tmp_new_sbox3 = 8'h4d;
+	8'he4: tmp_new_sbox3 = 8'hae;
+	8'he5: tmp_new_sbox3 = 8'h2a;
+	8'he6: tmp_new_sbox3 = 8'hf5;
+	8'he7: tmp_new_sbox3 = 8'hb0;
+	8'he8: tmp_new_sbox3 = 8'hc8;
+	8'he9: tmp_new_sbox3 = 8'heb;
+	8'hea: tmp_new_sbox3 = 8'hbb;
+	8'heb: tmp_new_sbox3 = 8'h3c;
+	8'hec: tmp_new_sbox3 = 8'h83;
+	8'hed: tmp_new_sbox3 = 8'h53;
+	8'hee: tmp_new_sbox3 = 8'h99;
+	8'hef: tmp_new_sbox3 = 8'h61;
+	8'hf0: tmp_new_sbox3 = 8'h17;
+	8'hf1: tmp_new_sbox3 = 8'h2b;
+	8'hf2: tmp_new_sbox3 = 8'h04;
+	8'hf3: tmp_new_sbox3 = 8'h7e;
+	8'hf4: tmp_new_sbox3 = 8'hba;
+	8'hf5: tmp_new_sbox3 = 8'h77;
+	8'hf6: tmp_new_sbox3 = 8'hd6;
+	8'hf7: tmp_new_sbox3 = 8'h26;
+	8'hf8: tmp_new_sbox3 = 8'he1;
+	8'hf9: tmp_new_sbox3 = 8'h69;
+	8'hfa: tmp_new_sbox3 = 8'h14;
+	8'hfb: tmp_new_sbox3 = 8'h63;
+	8'hfc: tmp_new_sbox3 = 8'h55;
+	8'hfd: tmp_new_sbox3 = 8'h21;
+	8'hfe: tmp_new_sbox3 = 8'h0c;
+	8'hff: tmp_new_sbox3 = 8'h7d;
+      endcase // case (sword)
+    end // inv_sbox_rom3
+
+endmodule // aes_inv_sbox
+
+//======================================================================
+// EOF aes_inv_sbox.v
+//======================================================================
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
new file mode 100644
index 0000000..e681c93
--- /dev/null
+++ b/src/rtl/aes_key_mem.v
@@ -0,0 +1,479 @@
+//======================================================================
+//
+// aes_key_mem.v
+// -------------
+// The AES key memort including round key generator.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_key_mem(
+                   input wire            clk,
+                   input wire            reset_n,
+
+                   input wire [255 : 0]  key,
+                   input wire            keylen,
+                   input wire            init,
+
+                   input wire    [3 : 0] round,
+                   output wire [127 : 0] round_key,
+                   output wire           ready,
+
+
+                   output wire [31 : 0]  sboxw,
+                   input wire  [31 : 0]  new_sboxw
+                  );
+
+
+  //----------------------------------------------------------------
+  // Parameters.
+  //----------------------------------------------------------------
+  parameter AES_128_BIT_KEY = 1'h0;
+  parameter AES_256_BIT_KEY = 1'h1;
+
+  parameter AES_128_NUM_ROUNDS = 4'ha;
+  parameter AES_256_NUM_ROUNDS = 4'he;
+
+  parameter CTRL_IDLE     = 3'h0;
+  parameter CTRL_INIT     = 3'h1;
+  parameter CTRL_GENERATE = 3'h2;
+  parameter CTRL_DONE     = 3'h3;
+
+
+  //----------------------------------------------------------------
+  // Registers.
+  //----------------------------------------------------------------
+  reg [127 : 0] key_mem [0 : 14];
+  reg [127 : 0] key_mem_new;
+  reg           key_mem_we;
+
+  reg [127 : 0] prev_key0_reg;
+  reg [127 : 0] prev_key0_new;
+  reg           prev_key0_we;
+
+  reg [127 : 0] prev_key1_reg;
+  reg [127 : 0] prev_key1_new;
+  reg           prev_key1_we;
+
+  reg [3 : 0] round_ctr_reg;
+  reg [3 : 0] round_ctr_new;
+  reg         round_ctr_rst;
+  reg         round_ctr_inc;
+  reg         round_ctr_we;
+
+  reg [2 : 0] key_mem_ctrl_reg;
+  reg [2 : 0] key_mem_ctrl_new;
+  reg         key_mem_ctrl_we;
+
+  reg         ready_reg;
+  reg         ready_new;
+  reg         ready_we;
+
+  reg [7 : 0] rcon_reg;
+  reg [7 : 0] rcon_new;
+  reg         rcon_we;
+  reg         rcon_set;
+  reg         rcon_next;
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [31 : 0] tmp_sboxw;
+
+  reg           round_key_update;
+  reg [3 : 0]   num_rounds;
+
+  reg [127 : 0] tmp_round_key;
+
+
+  //----------------------------------------------------------------
+  // Concurrent assignments for ports.
+  //----------------------------------------------------------------
+  assign round_key  = tmp_round_key;
+  assign ready      = ready_reg;
+  assign sboxw      = tmp_sboxw;
+
+
+  //----------------------------------------------------------------
+  // reg_update
+  //
+  // Update functionality for all registers in the core.
+  // All registers are positive edge triggered with asynchronous
+  // active low reset. All registers have write enable.
+  //----------------------------------------------------------------
+  always @ (posedge clk or negedge reset_n)
+    begin: reg_update
+      if (!reset_n)
+        begin
+          key_mem [0]      <= 128'h00000000000000000000000000000000;
+          key_mem [1]      <= 128'h00000000000000000000000000000000;
+          key_mem [2]      <= 128'h00000000000000000000000000000000;
+          key_mem [3]      <= 128'h00000000000000000000000000000000;
+          key_mem [4]      <= 128'h00000000000000000000000000000000;
+          key_mem [5]      <= 128'h00000000000000000000000000000000;
+          key_mem [6]      <= 128'h00000000000000000000000000000000;
+          key_mem [7]      <= 128'h00000000000000000000000000000000;
+          key_mem [8]      <= 128'h00000000000000000000000000000000;
+          key_mem [9]      <= 128'h00000000000000000000000000000000;
+          key_mem [10]     <= 128'h00000000000000000000000000000000;
+          key_mem [11]     <= 128'h00000000000000000000000000000000;
+          key_mem [12]     <= 128'h00000000000000000000000000000000;
+          key_mem [13]     <= 128'h00000000000000000000000000000000;
+          key_mem [14]     <= 128'h00000000000000000000000000000000;
+          prev_key0_reg    <= 128'h00000000000000000000000000000000;
+          prev_key1_reg    <= 128'h00000000000000000000000000000000;
+          rcon_reg         <= 8'h00;
+          ready_reg        <= 0;
+          round_ctr_reg    <= 4'h0;
+          key_mem_ctrl_reg <= CTRL_IDLE;
+        end
+      else
+        begin
+          if (round_ctr_we)
+            begin
+              round_ctr_reg <= round_ctr_new;
+            end
+
+          if (ready_we)
+            begin
+              ready_reg <= ready_new;
+            end
+
+          if (rcon_we)
+            begin
+              rcon_reg <= rcon_new;
+            end
+
+          if (key_mem_we)
+            begin
+              key_mem[round_ctr_reg] <= key_mem_new;
+            end
+
+          if (prev_key0_we)
+            begin
+              prev_key0_reg <= prev_key0_new;
+            end
+
+          if (prev_key1_we)
+            begin
+              prev_key1_reg <= prev_key1_new;
+            end
+
+          if (key_mem_ctrl_we)
+            begin
+              key_mem_ctrl_reg <= key_mem_ctrl_new;
+            end
+        end
+    end // reg_update
+
+
+  //----------------------------------------------------------------
+  // key_mem_read
+  //
+  // Combinational read port for the key memory.
+  //----------------------------------------------------------------
+  always @*
+    begin : key_mem_read
+      tmp_round_key = key_mem[round];
+    end // key_mem_read
+
+
+  //----------------------------------------------------------------
+  // round_key_gen
+  //
+  // The round key generator logic for AES-128 and AES-256.
+  //----------------------------------------------------------------
+  always @*
+    begin: round_key_gen
+      reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
+      reg [31 : 0] k0, k1, k2, k3;
+      reg [31 : 0] rconw, rotstw, tw, trw;
+
+      // Default assignments.
+      key_mem_new   = 128'h00000000000000000000000000000000;
+      key_mem_we    = 0;
+      prev_key0_new = 128'h00000000000000000000000000000000;
+      prev_key0_we  = 0;
+      prev_key1_new = 128'h00000000000000000000000000000000;
+      prev_key1_we  = 0;
+
+      k0 = 32'h00000000;
+      k1 = 32'h00000000;
+      k2 = 32'h00000000;
+      k3 = 32'h00000000;
+
+      rcon_set   = 1;
+      rcon_next  = 0;
+
+      // Extract words and calculate intermediate values.
+      // Perform rotation of sbox word etc.
+      w0 = prev_key0_reg[127 : 096];
+      w1 = prev_key0_reg[095 : 064];
+      w2 = prev_key0_reg[063 : 032];
+      w3 = prev_key0_reg[031 : 000];
+
+      w4 = prev_key1_reg[127 : 096];
+      w5 = prev_key1_reg[095 : 064];
+      w6 = prev_key1_reg[063 : 032];
+      w7 = prev_key1_reg[031 : 000];
+
+      rconw = {rcon_reg, 24'h000000};
+      tmp_sboxw = w7;
+      rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
+      trw = rotstw ^ rconw;
+      tw = new_sboxw;
+
+      // Generate the specific round keys.
+      if (round_key_update)
+        begin
+          rcon_set   = 0;
+          key_mem_we = 1;
+          case (keylen)
+            AES_128_BIT_KEY:
+              begin
+                if (round_ctr_reg == 0)
+                  begin
+                    key_mem_new   = key[255 : 128];
+                    prev_key1_new = key[255 : 128];
+                    prev_key1_we  = 1;
+                    rcon_next     = 1;
+                  end
+                else
+                  begin
+                    k0 = w4 ^ trw;
+                    k1 = w5 ^ w4 ^ trw;
+                    k2 = w6 ^ w5 ^ w4 ^ trw;
+                    k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
+
+                    key_mem_new   = {k0, k1, k2, k3};
+                    prev_key1_new = {k0, k1, k2, k3};
+                    prev_key1_we  = 1;
+                    rcon_next     = 1;
+                  end
+              end
+
+            AES_256_BIT_KEY:
+              begin
+                if (round_ctr_reg == 0)
+                  begin
+                    key_mem_new   = key[255 : 128];
+                    prev_key0_new = key[255 : 128];
+                    prev_key0_we  = 1;
+                  end
+                else if (round_ctr_reg == 1)
+                  begin
+                    key_mem_new   = key[127 : 0];
+                    prev_key1_new = key[127 : 0];
+                    prev_key1_we  = 1;
+                    rcon_next     = 1;
+                  end
+                else
+                  begin
+                    if (round_ctr_reg[0] == 0)
+                      begin
+                        k0 = w0 ^ trw;
+                        k1 = w1 ^ w0 ^ trw;
+                        k2 = w2 ^ w1 ^ w0 ^ trw;
+                        k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
+                      end
+                    else
+                      begin
+                        k0 = w0 ^ tw;
+                        k1 = w1 ^ w0 ^ tw;
+                        k2 = w2 ^ w1 ^ w0 ^ tw;
+                        k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
+                        rcon_next = 1;
+                      end
+
+                    // Store the generated round keys.
+                    key_mem_new   = {k0, k1, k2, k3};
+                    prev_key1_new = {k0, k1, k2, k3};
+                    prev_key1_we  = 1;
+                    prev_key0_new = prev_key1_reg;
+                    prev_key0_we  = 1;
+                  end
+              end
+
+            default:
+              begin
+              end
+          endcase // case (keylen)
+        end
+    end // round_key_gen
+
+
+  //----------------------------------------------------------------
+  // rcon_logic
+  //
+  // Caclulates the rcon value for the different key expansion
+  // iterations.
+  //----------------------------------------------------------------
+  always @*
+    begin : rcon_logic
+      reg [7 : 0] tmp_rcon;
+      rcon_new = 8'h00;
+      rcon_we  = 0;
+
+      tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
+
+      if (rcon_set)
+        begin
+          rcon_new = 8'h8d;
+          rcon_we  = 1;
+        end
+
+      if (rcon_next)
+        begin
+          rcon_new  = tmp_rcon[7 : 0];
+          rcon_we  = 1;
+        end
+    end
+
+
+  //----------------------------------------------------------------
+  // round_ctr
+  //
+  // The round counter logic with increase and reset.
+  //----------------------------------------------------------------
+  always @*
+    begin : round_ctr
+      round_ctr_new = 4'h0;
+      round_ctr_we  = 0;
+
+      if (round_ctr_rst)
+        begin
+          round_ctr_new = 4'h0;
+          round_ctr_we  = 1;
+        end
+
+      else if (round_ctr_inc)
+        begin
+          round_ctr_new = round_ctr_reg + 1'b1;
+          round_ctr_we  = 1;
+        end
+    end
+
+
+  //----------------------------------------------------------------
+  // num_rounds_logic
+  //
+  // Logic to select the number of rounds to generate keys for
+  //----------------------------------------------------------------
+  always @*
+    begin : num_rounds_logic
+      num_rounds = 4'h0;
+
+      case (keylen)
+        AES_128_BIT_KEY:
+          begin
+            num_rounds = AES_128_NUM_ROUNDS;
+          end
+
+        AES_256_BIT_KEY:
+          begin
+            num_rounds = AES_256_NUM_ROUNDS;
+          end
+
+        default:
+          begin
+          end
+      endcase // case (keylen)
+    end
+
+
+  //----------------------------------------------------------------
+  // key_mem_ctrl
+  //
+  //
+  // The FSM that controls the round key generation.
+  //----------------------------------------------------------------
+  always @*
+    begin: key_mem_ctrl
+      // Default assignments.
+      ready_new        = 0;
+      ready_we         = 0;
+      round_key_update = 0;
+      round_ctr_rst    = 0;
+      round_ctr_inc    = 0;
+      key_mem_ctrl_new = CTRL_IDLE;
+      key_mem_ctrl_we  = 0;
+
+      case(key_mem_ctrl_reg)
+        CTRL_IDLE:
+          begin
+            if (init)
+              begin
+                ready_new        = 0;
+                ready_we         = 1;
+                key_mem_ctrl_new = CTRL_INIT;
+                key_mem_ctrl_we  = 1;
+              end
+          end
+
+        CTRL_INIT:
+          begin
+            round_ctr_rst    = 1;
+            key_mem_ctrl_new = CTRL_GENERATE;
+            key_mem_ctrl_we  = 1;
+          end
+
+        CTRL_GENERATE:
+          begin
+            round_ctr_inc    = 1;
+            round_key_update = 1;
+            if (round_ctr_reg == num_rounds)
+              begin
+                key_mem_ctrl_new = CTRL_DONE;
+                key_mem_ctrl_we  = 1;
+              end
+          end
+
+        CTRL_DONE:
+          begin
+            ready_new        = 1;
+            ready_we         = 1;
+            key_mem_ctrl_new = CTRL_IDLE;
+            key_mem_ctrl_we  = 1;
+          end
+
+        default:
+          begin
+          end
+      endcase // case (key_mem_ctrl_reg)
+
+    end // key_mem_ctrl
+endmodule // aes_key_mem
+
+//======================================================================
+// EOF aes_key_mem.v
+//======================================================================
diff --git a/src/rtl/aes_sbox.v b/src/rtl/aes_sbox.v
new file mode 100644
index 0000000..2232ea8
--- /dev/null
+++ b/src/rtl/aes_sbox.v
@@ -0,0 +1,1137 @@
+//======================================================================
+//
+// aes_sbox.v
+// ----------
+// The AES S-box. Basically a 256 Byte ROM. This implementation
+// contains four parallel S-boxes to handle a 32 bit word.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_sbox(
+                input wire [31 : 0]  sboxw,
+                output wire [31 : 0] new_sboxw
+               );
+
+
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [7 : 0] tmp_new_sbox0;
+  reg [7 : 0] tmp_new_sbox1;
+  reg [7 : 0] tmp_new_sbox2;
+  reg [7 : 0] tmp_new_sbox3;
+
+
+  //----------------------------------------------------------------
+  // Concurrent assignments for ports.
+  //----------------------------------------------------------------
+  assign new_sboxw = {tmp_new_sbox0, tmp_new_sbox1,
+                      tmp_new_sbox2, tmp_new_sbox3};
+
+
+  //----------------------------------------------------------------
+  // sbox_rom0
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : sbox_rom0
+      case(sboxw[31 : 24])
+	   8'h00: tmp_new_sbox0 = 8'h63;
+	   8'h01: tmp_new_sbox0 = 8'h7c;
+	   8'h02: tmp_new_sbox0 = 8'h77;
+	   8'h03: tmp_new_sbox0 = 8'h7b;
+	   8'h04: tmp_new_sbox0 = 8'hf2;
+	   8'h05: tmp_new_sbox0 = 8'h6b;
+	   8'h06: tmp_new_sbox0 = 8'h6f;
+	   8'h07: tmp_new_sbox0 = 8'hc5;
+	   8'h08: tmp_new_sbox0 = 8'h30;
+	   8'h09: tmp_new_sbox0 = 8'h01;
+	   8'h0a: tmp_new_sbox0 = 8'h67;
+	   8'h0b: tmp_new_sbox0 = 8'h2b;
+	   8'h0c: tmp_new_sbox0 = 8'hfe;
+	   8'h0d: tmp_new_sbox0 = 8'hd7;
+	   8'h0e: tmp_new_sbox0 = 8'hab;
+	   8'h0f: tmp_new_sbox0 = 8'h76;
+	   8'h10: tmp_new_sbox0 = 8'hca;
+	   8'h11: tmp_new_sbox0 = 8'h82;
+	   8'h12: tmp_new_sbox0 = 8'hc9;
+	   8'h13: tmp_new_sbox0 = 8'h7d;
+	   8'h14: tmp_new_sbox0 = 8'hfa;
+	   8'h15: tmp_new_sbox0 = 8'h59;
+	   8'h16: tmp_new_sbox0 = 8'h47;
+	   8'h17: tmp_new_sbox0 = 8'hf0;
+	   8'h18: tmp_new_sbox0 = 8'had;
+	   8'h19: tmp_new_sbox0 = 8'hd4;
+	   8'h1a: tmp_new_sbox0 = 8'ha2;
+	   8'h1b: tmp_new_sbox0 = 8'haf;
+	   8'h1c: tmp_new_sbox0 = 8'h9c;
+	   8'h1d: tmp_new_sbox0 = 8'ha4;
+	   8'h1e: tmp_new_sbox0 = 8'h72;
+	   8'h1f: tmp_new_sbox0 = 8'hc0;
+	   8'h20: tmp_new_sbox0 = 8'hb7;
+	   8'h21: tmp_new_sbox0 = 8'hfd;
+	   8'h22: tmp_new_sbox0 = 8'h93;
+	   8'h23: tmp_new_sbox0 = 8'h26;
+	   8'h24: tmp_new_sbox0 = 8'h36;
+	   8'h25: tmp_new_sbox0 = 8'h3f;
+	   8'h26: tmp_new_sbox0 = 8'hf7;
+	   8'h27: tmp_new_sbox0 = 8'hcc;
+	   8'h28: tmp_new_sbox0 = 8'h34;
+	   8'h29: tmp_new_sbox0 = 8'ha5;
+	   8'h2a: tmp_new_sbox0 = 8'he5;
+	   8'h2b: tmp_new_sbox0 = 8'hf1;
+	   8'h2c: tmp_new_sbox0 = 8'h71;
+	   8'h2d: tmp_new_sbox0 = 8'hd8;
+	   8'h2e: tmp_new_sbox0 = 8'h31;
+	   8'h2f: tmp_new_sbox0 = 8'h15;
+	   8'h30: tmp_new_sbox0 = 8'h04;
+	   8'h31: tmp_new_sbox0 = 8'hc7;
+	   8'h32: tmp_new_sbox0 = 8'h23;
+	   8'h33: tmp_new_sbox0 = 8'hc3;
+	   8'h34: tmp_new_sbox0 = 8'h18;
+	   8'h35: tmp_new_sbox0 = 8'h96;
+	   8'h36: tmp_new_sbox0 = 8'h05;
+	   8'h37: tmp_new_sbox0 = 8'h9a;
+	   8'h38: tmp_new_sbox0 = 8'h07;
+	   8'h39: tmp_new_sbox0 = 8'h12;
+	   8'h3a: tmp_new_sbox0 = 8'h80;
+	   8'h3b: tmp_new_sbox0 = 8'he2;
+	   8'h3c: tmp_new_sbox0 = 8'heb;
+	   8'h3d: tmp_new_sbox0 = 8'h27;
+	   8'h3e: tmp_new_sbox0 = 8'hb2;
+	   8'h3f: tmp_new_sbox0 = 8'h75;
+	   8'h40: tmp_new_sbox0 = 8'h09;
+	   8'h41: tmp_new_sbox0 = 8'h83;
+	   8'h42: tmp_new_sbox0 = 8'h2c;
+	   8'h43: tmp_new_sbox0 = 8'h1a;
+	   8'h44: tmp_new_sbox0 = 8'h1b;
+	   8'h45: tmp_new_sbox0 = 8'h6e;
+	   8'h46: tmp_new_sbox0 = 8'h5a;
+	   8'h47: tmp_new_sbox0 = 8'ha0;
+	   8'h48: tmp_new_sbox0 = 8'h52;
+	   8'h49: tmp_new_sbox0 = 8'h3b;
+	   8'h4a: tmp_new_sbox0 = 8'hd6;
+	   8'h4b: tmp_new_sbox0 = 8'hb3;
+	   8'h4c: tmp_new_sbox0 = 8'h29;
+	   8'h4d: tmp_new_sbox0 = 8'he3;
+	   8'h4e: tmp_new_sbox0 = 8'h2f;
+	   8'h4f: tmp_new_sbox0 = 8'h84;
+	   8'h50: tmp_new_sbox0 = 8'h53;
+	   8'h51: tmp_new_sbox0 = 8'hd1;
+	   8'h52: tmp_new_sbox0 = 8'h00;
+	   8'h53: tmp_new_sbox0 = 8'hed;
+	   8'h54: tmp_new_sbox0 = 8'h20;
+	   8'h55: tmp_new_sbox0 = 8'hfc;
+	   8'h56: tmp_new_sbox0 = 8'hb1;
+	   8'h57: tmp_new_sbox0 = 8'h5b;
+	   8'h58: tmp_new_sbox0 = 8'h6a;
+	   8'h59: tmp_new_sbox0 = 8'hcb;
+	   8'h5a: tmp_new_sbox0 = 8'hbe;
+	   8'h5b: tmp_new_sbox0 = 8'h39;
+	   8'h5c: tmp_new_sbox0 = 8'h4a;
+	   8'h5d: tmp_new_sbox0 = 8'h4c;
+	   8'h5e: tmp_new_sbox0 = 8'h58;
+	   8'h5f: tmp_new_sbox0 = 8'hcf;
+	   8'h60: tmp_new_sbox0 = 8'hd0;
+	   8'h61: tmp_new_sbox0 = 8'hef;
+	   8'h62: tmp_new_sbox0 = 8'haa;
+	   8'h63: tmp_new_sbox0 = 8'hfb;
+	   8'h64: tmp_new_sbox0 = 8'h43;
+	   8'h65: tmp_new_sbox0 = 8'h4d;
+	   8'h66: tmp_new_sbox0 = 8'h33;
+	   8'h67: tmp_new_sbox0 = 8'h85;
+	   8'h68: tmp_new_sbox0 = 8'h45;
+	   8'h69: tmp_new_sbox0 = 8'hf9;
+	   8'h6a: tmp_new_sbox0 = 8'h02;
+	   8'h6b: tmp_new_sbox0 = 8'h7f;
+	   8'h6c: tmp_new_sbox0 = 8'h50;
+	   8'h6d: tmp_new_sbox0 = 8'h3c;
+	   8'h6e: tmp_new_sbox0 = 8'h9f;
+	   8'h6f: tmp_new_sbox0 = 8'ha8;
+	   8'h70: tmp_new_sbox0 = 8'h51;
+	   8'h71: tmp_new_sbox0 = 8'ha3;
+	   8'h72: tmp_new_sbox0 = 8'h40;
+	   8'h73: tmp_new_sbox0 = 8'h8f;
+	   8'h74: tmp_new_sbox0 = 8'h92;
+	   8'h75: tmp_new_sbox0 = 8'h9d;
+	   8'h76: tmp_new_sbox0 = 8'h38;
+	   8'h77: tmp_new_sbox0 = 8'hf5;
+	   8'h78: tmp_new_sbox0 = 8'hbc;
+	   8'h79: tmp_new_sbox0 = 8'hb6;
+	   8'h7a: tmp_new_sbox0 = 8'hda;
+	   8'h7b: tmp_new_sbox0 = 8'h21;
+	   8'h7c: tmp_new_sbox0 = 8'h10;
+	   8'h7d: tmp_new_sbox0 = 8'hff;
+	   8'h7e: tmp_new_sbox0 = 8'hf3;
+	   8'h7f: tmp_new_sbox0 = 8'hd2;
+	   8'h80: tmp_new_sbox0 = 8'hcd;
+	   8'h81: tmp_new_sbox0 = 8'h0c;
+	   8'h82: tmp_new_sbox0 = 8'h13;
+	   8'h83: tmp_new_sbox0 = 8'hec;
+	   8'h84: tmp_new_sbox0 = 8'h5f;
+	   8'h85: tmp_new_sbox0 = 8'h97;
+	   8'h86: tmp_new_sbox0 = 8'h44;
+	   8'h87: tmp_new_sbox0 = 8'h17;
+	   8'h88: tmp_new_sbox0 = 8'hc4;
+	   8'h89: tmp_new_sbox0 = 8'ha7;
+	   8'h8a: tmp_new_sbox0 = 8'h7e;
+	   8'h8b: tmp_new_sbox0 = 8'h3d;
+	   8'h8c: tmp_new_sbox0 = 8'h64;
+	   8'h8d: tmp_new_sbox0 = 8'h5d;
+	   8'h8e: tmp_new_sbox0 = 8'h19;
+	   8'h8f: tmp_new_sbox0 = 8'h73;
+	   8'h90: tmp_new_sbox0 = 8'h60;
+	   8'h91: tmp_new_sbox0 = 8'h81;
+	   8'h92: tmp_new_sbox0 = 8'h4f;
+	   8'h93: tmp_new_sbox0 = 8'hdc;
+	   8'h94: tmp_new_sbox0 = 8'h22;
+	   8'h95: tmp_new_sbox0 = 8'h2a;
+	   8'h96: tmp_new_sbox0 = 8'h90;
+	   8'h97: tmp_new_sbox0 = 8'h88;
+	   8'h98: tmp_new_sbox0 = 8'h46;
+	   8'h99: tmp_new_sbox0 = 8'hee;
+	   8'h9a: tmp_new_sbox0 = 8'hb8;
+	   8'h9b: tmp_new_sbox0 = 8'h14;
+	   8'h9c: tmp_new_sbox0 = 8'hde;
+	   8'h9d: tmp_new_sbox0 = 8'h5e;
+	   8'h9e: tmp_new_sbox0 = 8'h0b;
+	   8'h9f: tmp_new_sbox0 = 8'hdb;
+	   8'ha0: tmp_new_sbox0 = 8'he0;
+	   8'ha1: tmp_new_sbox0 = 8'h32;
+	   8'ha2: tmp_new_sbox0 = 8'h3a;
+	   8'ha3: tmp_new_sbox0 = 8'h0a;
+	   8'ha4: tmp_new_sbox0 = 8'h49;
+	   8'ha5: tmp_new_sbox0 = 8'h06;
+	   8'ha6: tmp_new_sbox0 = 8'h24;
+	   8'ha7: tmp_new_sbox0 = 8'h5c;
+	   8'ha8: tmp_new_sbox0 = 8'hc2;
+	   8'ha9: tmp_new_sbox0 = 8'hd3;
+	   8'haa: tmp_new_sbox0 = 8'hac;
+	   8'hab: tmp_new_sbox0 = 8'h62;
+	   8'hac: tmp_new_sbox0 = 8'h91;
+	   8'had: tmp_new_sbox0 = 8'h95;
+	   8'hae: tmp_new_sbox0 = 8'he4;
+	   8'haf: tmp_new_sbox0 = 8'h79;
+	   8'hb0: tmp_new_sbox0 = 8'he7;
+	   8'hb1: tmp_new_sbox0 = 8'hc8;
+	   8'hb2: tmp_new_sbox0 = 8'h37;
+	   8'hb3: tmp_new_sbox0 = 8'h6d;
+	   8'hb4: tmp_new_sbox0 = 8'h8d;
+	   8'hb5: tmp_new_sbox0 = 8'hd5;
+	   8'hb6: tmp_new_sbox0 = 8'h4e;
+	   8'hb7: tmp_new_sbox0 = 8'ha9;
+	   8'hb8: tmp_new_sbox0 = 8'h6c;
+	   8'hb9: tmp_new_sbox0 = 8'h56;
+	   8'hba: tmp_new_sbox0 = 8'hf4;
+	   8'hbb: tmp_new_sbox0 = 8'hea;
+	   8'hbc: tmp_new_sbox0 = 8'h65;
+	   8'hbd: tmp_new_sbox0 = 8'h7a;
+	   8'hbe: tmp_new_sbox0 = 8'hae;
+	   8'hbf: tmp_new_sbox0 = 8'h08;
+	   8'hc0: tmp_new_sbox0 = 8'hba;
+	   8'hc1: tmp_new_sbox0 = 8'h78;
+	   8'hc2: tmp_new_sbox0 = 8'h25;
+	   8'hc3: tmp_new_sbox0 = 8'h2e;
+	   8'hc4: tmp_new_sbox0 = 8'h1c;
+	   8'hc5: tmp_new_sbox0 = 8'ha6;
+	   8'hc6: tmp_new_sbox0 = 8'hb4;
+	   8'hc7: tmp_new_sbox0 = 8'hc6;
+	   8'hc8: tmp_new_sbox0 = 8'he8;
+	   8'hc9: tmp_new_sbox0 = 8'hdd;
+	   8'hca: tmp_new_sbox0 = 8'h74;
+	   8'hcb: tmp_new_sbox0 = 8'h1f;
+	   8'hcc: tmp_new_sbox0 = 8'h4b;
+	   8'hcd: tmp_new_sbox0 = 8'hbd;
+	   8'hce: tmp_new_sbox0 = 8'h8b;
+	   8'hcf: tmp_new_sbox0 = 8'h8a;
+	   8'hd0: tmp_new_sbox0 = 8'h70;
+	   8'hd1: tmp_new_sbox0 = 8'h3e;
+	   8'hd2: tmp_new_sbox0 = 8'hb5;
+	   8'hd3: tmp_new_sbox0 = 8'h66;
+	   8'hd4: tmp_new_sbox0 = 8'h48;
+	   8'hd5: tmp_new_sbox0 = 8'h03;
+	   8'hd6: tmp_new_sbox0 = 8'hf6;
+	   8'hd7: tmp_new_sbox0 = 8'h0e;
+	   8'hd8: tmp_new_sbox0 = 8'h61;
+	   8'hd9: tmp_new_sbox0 = 8'h35;
+	   8'hda: tmp_new_sbox0 = 8'h57;
+	   8'hdb: tmp_new_sbox0 = 8'hb9;
+	   8'hdc: tmp_new_sbox0 = 8'h86;
+	   8'hdd: tmp_new_sbox0 = 8'hc1;
+	   8'hde: tmp_new_sbox0 = 8'h1d;
+	   8'hdf: tmp_new_sbox0 = 8'h9e;
+	   8'he0: tmp_new_sbox0 = 8'he1;
+	   8'he1: tmp_new_sbox0 = 8'hf8;
+	   8'he2: tmp_new_sbox0 = 8'h98;
+	   8'he3: tmp_new_sbox0 = 8'h11;
+	   8'he4: tmp_new_sbox0 = 8'h69;
+	   8'he5: tmp_new_sbox0 = 8'hd9;
+	   8'he6: tmp_new_sbox0 = 8'h8e;
+	   8'he7: tmp_new_sbox0 = 8'h94;
+	   8'he8: tmp_new_sbox0 = 8'h9b;
+	   8'he9: tmp_new_sbox0 = 8'h1e;
+	   8'hea: tmp_new_sbox0 = 8'h87;
+	   8'heb: tmp_new_sbox0 = 8'he9;
+	   8'hec: tmp_new_sbox0 = 8'hce;
+	   8'hed: tmp_new_sbox0 = 8'h55;
+	   8'hee: tmp_new_sbox0 = 8'h28;
+	   8'hef: tmp_new_sbox0 = 8'hdf;
+	   8'hf0: tmp_new_sbox0 = 8'h8c;
+	   8'hf1: tmp_new_sbox0 = 8'ha1;
+	   8'hf2: tmp_new_sbox0 = 8'h89;
+	   8'hf3: tmp_new_sbox0 = 8'h0d;
+	   8'hf4: tmp_new_sbox0 = 8'hbf;
+	   8'hf5: tmp_new_sbox0 = 8'he6;
+	   8'hf6: tmp_new_sbox0 = 8'h42;
+	   8'hf7: tmp_new_sbox0 = 8'h68;
+	   8'hf8: tmp_new_sbox0 = 8'h41;
+	   8'hf9: tmp_new_sbox0 = 8'h99;
+	   8'hfa: tmp_new_sbox0 = 8'h2d;
+	   8'hfb: tmp_new_sbox0 = 8'h0f;
+	   8'hfc: tmp_new_sbox0 = 8'hb0;
+	   8'hfd: tmp_new_sbox0 = 8'h54;
+	   8'hfe: tmp_new_sbox0 = 8'hbb;
+	   8'hff: tmp_new_sbox0 = 8'h16;
+      endcase // case (sboxw[31 : 24])
+    end // sbox_rom0
+
+
+  //----------------------------------------------------------------
+  // sbox_rom1
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : sbox_rom1
+      case(sboxw[23 : 16])
+	   8'h00: tmp_new_sbox1 = 8'h63;
+	   8'h01: tmp_new_sbox1 = 8'h7c;
+	   8'h02: tmp_new_sbox1 = 8'h77;
+	   8'h03: tmp_new_sbox1 = 8'h7b;
+	   8'h04: tmp_new_sbox1 = 8'hf2;
+	   8'h05: tmp_new_sbox1 = 8'h6b;
+	   8'h06: tmp_new_sbox1 = 8'h6f;
+	   8'h07: tmp_new_sbox1 = 8'hc5;
+	   8'h08: tmp_new_sbox1 = 8'h30;
+	   8'h09: tmp_new_sbox1 = 8'h01;
+	   8'h0a: tmp_new_sbox1 = 8'h67;
+	   8'h0b: tmp_new_sbox1 = 8'h2b;
+	   8'h0c: tmp_new_sbox1 = 8'hfe;
+	   8'h0d: tmp_new_sbox1 = 8'hd7;
+	   8'h0e: tmp_new_sbox1 = 8'hab;
+	   8'h0f: tmp_new_sbox1 = 8'h76;
+	   8'h10: tmp_new_sbox1 = 8'hca;
+	   8'h11: tmp_new_sbox1 = 8'h82;
+	   8'h12: tmp_new_sbox1 = 8'hc9;
+	   8'h13: tmp_new_sbox1 = 8'h7d;
+	   8'h14: tmp_new_sbox1 = 8'hfa;
+	   8'h15: tmp_new_sbox1 = 8'h59;
+	   8'h16: tmp_new_sbox1 = 8'h47;
+	   8'h17: tmp_new_sbox1 = 8'hf0;
+	   8'h18: tmp_new_sbox1 = 8'had;
+	   8'h19: tmp_new_sbox1 = 8'hd4;
+	   8'h1a: tmp_new_sbox1 = 8'ha2;
+	   8'h1b: tmp_new_sbox1 = 8'haf;
+	   8'h1c: tmp_new_sbox1 = 8'h9c;
+	   8'h1d: tmp_new_sbox1 = 8'ha4;
+	   8'h1e: tmp_new_sbox1 = 8'h72;
+	   8'h1f: tmp_new_sbox1 = 8'hc0;
+	   8'h20: tmp_new_sbox1 = 8'hb7;
+	   8'h21: tmp_new_sbox1 = 8'hfd;
+	   8'h22: tmp_new_sbox1 = 8'h93;
+	   8'h23: tmp_new_sbox1 = 8'h26;
+	   8'h24: tmp_new_sbox1 = 8'h36;
+	   8'h25: tmp_new_sbox1 = 8'h3f;
+	   8'h26: tmp_new_sbox1 = 8'hf7;
+	   8'h27: tmp_new_sbox1 = 8'hcc;
+	   8'h28: tmp_new_sbox1 = 8'h34;
+	   8'h29: tmp_new_sbox1 = 8'ha5;
+	   8'h2a: tmp_new_sbox1 = 8'he5;
+	   8'h2b: tmp_new_sbox1 = 8'hf1;
+	   8'h2c: tmp_new_sbox1 = 8'h71;
+	   8'h2d: tmp_new_sbox1 = 8'hd8;
+	   8'h2e: tmp_new_sbox1 = 8'h31;
+	   8'h2f: tmp_new_sbox1 = 8'h15;
+	   8'h30: tmp_new_sbox1 = 8'h04;
+	   8'h31: tmp_new_sbox1 = 8'hc7;
+	   8'h32: tmp_new_sbox1 = 8'h23;
+	   8'h33: tmp_new_sbox1 = 8'hc3;
+	   8'h34: tmp_new_sbox1 = 8'h18;
+	   8'h35: tmp_new_sbox1 = 8'h96;
+	   8'h36: tmp_new_sbox1 = 8'h05;
+	   8'h37: tmp_new_sbox1 = 8'h9a;
+	   8'h38: tmp_new_sbox1 = 8'h07;
+	   8'h39: tmp_new_sbox1 = 8'h12;
+	   8'h3a: tmp_new_sbox1 = 8'h80;
+	   8'h3b: tmp_new_sbox1 = 8'he2;
+	   8'h3c: tmp_new_sbox1 = 8'heb;
+	   8'h3d: tmp_new_sbox1 = 8'h27;
+	   8'h3e: tmp_new_sbox1 = 8'hb2;
+	   8'h3f: tmp_new_sbox1 = 8'h75;
+	   8'h40: tmp_new_sbox1 = 8'h09;
+	   8'h41: tmp_new_sbox1 = 8'h83;
+	   8'h42: tmp_new_sbox1 = 8'h2c;
+	   8'h43: tmp_new_sbox1 = 8'h1a;
+	   8'h44: tmp_new_sbox1 = 8'h1b;
+	   8'h45: tmp_new_sbox1 = 8'h6e;
+	   8'h46: tmp_new_sbox1 = 8'h5a;
+	   8'h47: tmp_new_sbox1 = 8'ha0;
+	   8'h48: tmp_new_sbox1 = 8'h52;
+	   8'h49: tmp_new_sbox1 = 8'h3b;
+	   8'h4a: tmp_new_sbox1 = 8'hd6;
+	   8'h4b: tmp_new_sbox1 = 8'hb3;
+	   8'h4c: tmp_new_sbox1 = 8'h29;
+	   8'h4d: tmp_new_sbox1 = 8'he3;
+	   8'h4e: tmp_new_sbox1 = 8'h2f;
+	   8'h4f: tmp_new_sbox1 = 8'h84;
+	   8'h50: tmp_new_sbox1 = 8'h53;
+	   8'h51: tmp_new_sbox1 = 8'hd1;
+	   8'h52: tmp_new_sbox1 = 8'h00;
+	   8'h53: tmp_new_sbox1 = 8'hed;
+	   8'h54: tmp_new_sbox1 = 8'h20;
+	   8'h55: tmp_new_sbox1 = 8'hfc;
+	   8'h56: tmp_new_sbox1 = 8'hb1;
+	   8'h57: tmp_new_sbox1 = 8'h5b;
+	   8'h58: tmp_new_sbox1 = 8'h6a;
+	   8'h59: tmp_new_sbox1 = 8'hcb;
+	   8'h5a: tmp_new_sbox1 = 8'hbe;
+	   8'h5b: tmp_new_sbox1 = 8'h39;
+	   8'h5c: tmp_new_sbox1 = 8'h4a;
+	   8'h5d: tmp_new_sbox1 = 8'h4c;
+	   8'h5e: tmp_new_sbox1 = 8'h58;
+	   8'h5f: tmp_new_sbox1 = 8'hcf;
+	   8'h60: tmp_new_sbox1 = 8'hd0;
+	   8'h61: tmp_new_sbox1 = 8'hef;
+	   8'h62: tmp_new_sbox1 = 8'haa;
+	   8'h63: tmp_new_sbox1 = 8'hfb;
+	   8'h64: tmp_new_sbox1 = 8'h43;
+	   8'h65: tmp_new_sbox1 = 8'h4d;
+	   8'h66: tmp_new_sbox1 = 8'h33;
+	   8'h67: tmp_new_sbox1 = 8'h85;
+	   8'h68: tmp_new_sbox1 = 8'h45;
+	   8'h69: tmp_new_sbox1 = 8'hf9;
+	   8'h6a: tmp_new_sbox1 = 8'h02;
+	   8'h6b: tmp_new_sbox1 = 8'h7f;
+	   8'h6c: tmp_new_sbox1 = 8'h50;
+	   8'h6d: tmp_new_sbox1 = 8'h3c;
+	   8'h6e: tmp_new_sbox1 = 8'h9f;
+	   8'h6f: tmp_new_sbox1 = 8'ha8;
+	   8'h70: tmp_new_sbox1 = 8'h51;
+	   8'h71: tmp_new_sbox1 = 8'ha3;
+	   8'h72: tmp_new_sbox1 = 8'h40;
+	   8'h73: tmp_new_sbox1 = 8'h8f;
+	   8'h74: tmp_new_sbox1 = 8'h92;
+	   8'h75: tmp_new_sbox1 = 8'h9d;
+	   8'h76: tmp_new_sbox1 = 8'h38;
+	   8'h77: tmp_new_sbox1 = 8'hf5;
+	   8'h78: tmp_new_sbox1 = 8'hbc;
+	   8'h79: tmp_new_sbox1 = 8'hb6;
+	   8'h7a: tmp_new_sbox1 = 8'hda;
+	   8'h7b: tmp_new_sbox1 = 8'h21;
+	   8'h7c: tmp_new_sbox1 = 8'h10;
+	   8'h7d: tmp_new_sbox1 = 8'hff;
+	   8'h7e: tmp_new_sbox1 = 8'hf3;
+	   8'h7f: tmp_new_sbox1 = 8'hd2;
+	   8'h80: tmp_new_sbox1 = 8'hcd;
+	   8'h81: tmp_new_sbox1 = 8'h0c;
+	   8'h82: tmp_new_sbox1 = 8'h13;
+	   8'h83: tmp_new_sbox1 = 8'hec;
+	   8'h84: tmp_new_sbox1 = 8'h5f;
+	   8'h85: tmp_new_sbox1 = 8'h97;
+	   8'h86: tmp_new_sbox1 = 8'h44;
+	   8'h87: tmp_new_sbox1 = 8'h17;
+	   8'h88: tmp_new_sbox1 = 8'hc4;
+	   8'h89: tmp_new_sbox1 = 8'ha7;
+	   8'h8a: tmp_new_sbox1 = 8'h7e;
+	   8'h8b: tmp_new_sbox1 = 8'h3d;
+	   8'h8c: tmp_new_sbox1 = 8'h64;
+	   8'h8d: tmp_new_sbox1 = 8'h5d;
+	   8'h8e: tmp_new_sbox1 = 8'h19;
+	   8'h8f: tmp_new_sbox1 = 8'h73;
+	   8'h90: tmp_new_sbox1 = 8'h60;
+	   8'h91: tmp_new_sbox1 = 8'h81;
+	   8'h92: tmp_new_sbox1 = 8'h4f;
+	   8'h93: tmp_new_sbox1 = 8'hdc;
+	   8'h94: tmp_new_sbox1 = 8'h22;
+	   8'h95: tmp_new_sbox1 = 8'h2a;
+	   8'h96: tmp_new_sbox1 = 8'h90;
+	   8'h97: tmp_new_sbox1 = 8'h88;
+	   8'h98: tmp_new_sbox1 = 8'h46;
+	   8'h99: tmp_new_sbox1 = 8'hee;
+	   8'h9a: tmp_new_sbox1 = 8'hb8;
+	   8'h9b: tmp_new_sbox1 = 8'h14;
+	   8'h9c: tmp_new_sbox1 = 8'hde;
+	   8'h9d: tmp_new_sbox1 = 8'h5e;
+	   8'h9e: tmp_new_sbox1 = 8'h0b;
+	   8'h9f: tmp_new_sbox1 = 8'hdb;
+	   8'ha0: tmp_new_sbox1 = 8'he0;
+	   8'ha1: tmp_new_sbox1 = 8'h32;
+	   8'ha2: tmp_new_sbox1 = 8'h3a;
+	   8'ha3: tmp_new_sbox1 = 8'h0a;
+	   8'ha4: tmp_new_sbox1 = 8'h49;
+	   8'ha5: tmp_new_sbox1 = 8'h06;
+	   8'ha6: tmp_new_sbox1 = 8'h24;
+	   8'ha7: tmp_new_sbox1 = 8'h5c;
+	   8'ha8: tmp_new_sbox1 = 8'hc2;
+	   8'ha9: tmp_new_sbox1 = 8'hd3;
+	   8'haa: tmp_new_sbox1 = 8'hac;
+	   8'hab: tmp_new_sbox1 = 8'h62;
+	   8'hac: tmp_new_sbox1 = 8'h91;
+	   8'had: tmp_new_sbox1 = 8'h95;
+	   8'hae: tmp_new_sbox1 = 8'he4;
+	   8'haf: tmp_new_sbox1 = 8'h79;
+	   8'hb0: tmp_new_sbox1 = 8'he7;
+	   8'hb1: tmp_new_sbox1 = 8'hc8;
+	   8'hb2: tmp_new_sbox1 = 8'h37;
+	   8'hb3: tmp_new_sbox1 = 8'h6d;
+	   8'hb4: tmp_new_sbox1 = 8'h8d;
+	   8'hb5: tmp_new_sbox1 = 8'hd5;
+	   8'hb6: tmp_new_sbox1 = 8'h4e;
+	   8'hb7: tmp_new_sbox1 = 8'ha9;
+	   8'hb8: tmp_new_sbox1 = 8'h6c;
+	   8'hb9: tmp_new_sbox1 = 8'h56;
+	   8'hba: tmp_new_sbox1 = 8'hf4;
+	   8'hbb: tmp_new_sbox1 = 8'hea;
+	   8'hbc: tmp_new_sbox1 = 8'h65;
+	   8'hbd: tmp_new_sbox1 = 8'h7a;
+	   8'hbe: tmp_new_sbox1 = 8'hae;
+	   8'hbf: tmp_new_sbox1 = 8'h08;
+	   8'hc0: tmp_new_sbox1 = 8'hba;
+	   8'hc1: tmp_new_sbox1 = 8'h78;
+	   8'hc2: tmp_new_sbox1 = 8'h25;
+	   8'hc3: tmp_new_sbox1 = 8'h2e;
+	   8'hc4: tmp_new_sbox1 = 8'h1c;
+	   8'hc5: tmp_new_sbox1 = 8'ha6;
+	   8'hc6: tmp_new_sbox1 = 8'hb4;
+	   8'hc7: tmp_new_sbox1 = 8'hc6;
+	   8'hc8: tmp_new_sbox1 = 8'he8;
+	   8'hc9: tmp_new_sbox1 = 8'hdd;
+	   8'hca: tmp_new_sbox1 = 8'h74;
+	   8'hcb: tmp_new_sbox1 = 8'h1f;
+	   8'hcc: tmp_new_sbox1 = 8'h4b;
+	   8'hcd: tmp_new_sbox1 = 8'hbd;
+	   8'hce: tmp_new_sbox1 = 8'h8b;
+	   8'hcf: tmp_new_sbox1 = 8'h8a;
+	   8'hd0: tmp_new_sbox1 = 8'h70;
+	   8'hd1: tmp_new_sbox1 = 8'h3e;
+	   8'hd2: tmp_new_sbox1 = 8'hb5;
+	   8'hd3: tmp_new_sbox1 = 8'h66;
+	   8'hd4: tmp_new_sbox1 = 8'h48;
+	   8'hd5: tmp_new_sbox1 = 8'h03;
+	   8'hd6: tmp_new_sbox1 = 8'hf6;
+	   8'hd7: tmp_new_sbox1 = 8'h0e;
+	   8'hd8: tmp_new_sbox1 = 8'h61;
+	   8'hd9: tmp_new_sbox1 = 8'h35;
+	   8'hda: tmp_new_sbox1 = 8'h57;
+	   8'hdb: tmp_new_sbox1 = 8'hb9;
+	   8'hdc: tmp_new_sbox1 = 8'h86;
+	   8'hdd: tmp_new_sbox1 = 8'hc1;
+	   8'hde: tmp_new_sbox1 = 8'h1d;
+	   8'hdf: tmp_new_sbox1 = 8'h9e;
+	   8'he0: tmp_new_sbox1 = 8'he1;
+	   8'he1: tmp_new_sbox1 = 8'hf8;
+	   8'he2: tmp_new_sbox1 = 8'h98;
+	   8'he3: tmp_new_sbox1 = 8'h11;
+	   8'he4: tmp_new_sbox1 = 8'h69;
+	   8'he5: tmp_new_sbox1 = 8'hd9;
+	   8'he6: tmp_new_sbox1 = 8'h8e;
+	   8'he7: tmp_new_sbox1 = 8'h94;
+	   8'he8: tmp_new_sbox1 = 8'h9b;
+	   8'he9: tmp_new_sbox1 = 8'h1e;
+	   8'hea: tmp_new_sbox1 = 8'h87;
+	   8'heb: tmp_new_sbox1 = 8'he9;
+	   8'hec: tmp_new_sbox1 = 8'hce;
+	   8'hed: tmp_new_sbox1 = 8'h55;
+	   8'hee: tmp_new_sbox1 = 8'h28;
+	   8'hef: tmp_new_sbox1 = 8'hdf;
+	   8'hf0: tmp_new_sbox1 = 8'h8c;
+	   8'hf1: tmp_new_sbox1 = 8'ha1;
+	   8'hf2: tmp_new_sbox1 = 8'h89;
+	   8'hf3: tmp_new_sbox1 = 8'h0d;
+	   8'hf4: tmp_new_sbox1 = 8'hbf;
+	   8'hf5: tmp_new_sbox1 = 8'he6;
+	   8'hf6: tmp_new_sbox1 = 8'h42;
+	   8'hf7: tmp_new_sbox1 = 8'h68;
+	   8'hf8: tmp_new_sbox1 = 8'h41;
+	   8'hf9: tmp_new_sbox1 = 8'h99;
+	   8'hfa: tmp_new_sbox1 = 8'h2d;
+	   8'hfb: tmp_new_sbox1 = 8'h0f;
+	   8'hfc: tmp_new_sbox1 = 8'hb0;
+	   8'hfd: tmp_new_sbox1 = 8'h54;
+	   8'hfe: tmp_new_sbox1 = 8'hbb;
+	   8'hff: tmp_new_sbox1 = 8'h16;
+      endcase // case (sboxw[23 : 16])
+    end // sbox_rom1
+
+
+  //----------------------------------------------------------------
+  // sbox_rom2
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : sbox_rom2
+      case(sboxw[15 : 8])
+	   8'h00: tmp_new_sbox2 = 8'h63;
+	   8'h01: tmp_new_sbox2 = 8'h7c;
+	   8'h02: tmp_new_sbox2 = 8'h77;
+	   8'h03: tmp_new_sbox2 = 8'h7b;
+	   8'h04: tmp_new_sbox2 = 8'hf2;
+	   8'h05: tmp_new_sbox2 = 8'h6b;
+	   8'h06: tmp_new_sbox2 = 8'h6f;
+	   8'h07: tmp_new_sbox2 = 8'hc5;
+	   8'h08: tmp_new_sbox2 = 8'h30;
+	   8'h09: tmp_new_sbox2 = 8'h01;
+	   8'h0a: tmp_new_sbox2 = 8'h67;
+	   8'h0b: tmp_new_sbox2 = 8'h2b;
+	   8'h0c: tmp_new_sbox2 = 8'hfe;
+	   8'h0d: tmp_new_sbox2 = 8'hd7;
+	   8'h0e: tmp_new_sbox2 = 8'hab;
+	   8'h0f: tmp_new_sbox2 = 8'h76;
+	   8'h10: tmp_new_sbox2 = 8'hca;
+	   8'h11: tmp_new_sbox2 = 8'h82;
+	   8'h12: tmp_new_sbox2 = 8'hc9;
+	   8'h13: tmp_new_sbox2 = 8'h7d;
+	   8'h14: tmp_new_sbox2 = 8'hfa;
+	   8'h15: tmp_new_sbox2 = 8'h59;
+	   8'h16: tmp_new_sbox2 = 8'h47;
+	   8'h17: tmp_new_sbox2 = 8'hf0;
+	   8'h18: tmp_new_sbox2 = 8'had;
+	   8'h19: tmp_new_sbox2 = 8'hd4;
+	   8'h1a: tmp_new_sbox2 = 8'ha2;
+	   8'h1b: tmp_new_sbox2 = 8'haf;
+	   8'h1c: tmp_new_sbox2 = 8'h9c;
+	   8'h1d: tmp_new_sbox2 = 8'ha4;
+	   8'h1e: tmp_new_sbox2 = 8'h72;
+	   8'h1f: tmp_new_sbox2 = 8'hc0;
+	   8'h20: tmp_new_sbox2 = 8'hb7;
+	   8'h21: tmp_new_sbox2 = 8'hfd;
+	   8'h22: tmp_new_sbox2 = 8'h93;
+	   8'h23: tmp_new_sbox2 = 8'h26;
+	   8'h24: tmp_new_sbox2 = 8'h36;
+	   8'h25: tmp_new_sbox2 = 8'h3f;
+	   8'h26: tmp_new_sbox2 = 8'hf7;
+	   8'h27: tmp_new_sbox2 = 8'hcc;
+	   8'h28: tmp_new_sbox2 = 8'h34;
+	   8'h29: tmp_new_sbox2 = 8'ha5;
+	   8'h2a: tmp_new_sbox2 = 8'he5;
+	   8'h2b: tmp_new_sbox2 = 8'hf1;
+	   8'h2c: tmp_new_sbox2 = 8'h71;
+	   8'h2d: tmp_new_sbox2 = 8'hd8;
+	   8'h2e: tmp_new_sbox2 = 8'h31;
+	   8'h2f: tmp_new_sbox2 = 8'h15;
+	   8'h30: tmp_new_sbox2 = 8'h04;
+	   8'h31: tmp_new_sbox2 = 8'hc7;
+	   8'h32: tmp_new_sbox2 = 8'h23;
+	   8'h33: tmp_new_sbox2 = 8'hc3;
+	   8'h34: tmp_new_sbox2 = 8'h18;
+	   8'h35: tmp_new_sbox2 = 8'h96;
+	   8'h36: tmp_new_sbox2 = 8'h05;
+	   8'h37: tmp_new_sbox2 = 8'h9a;
+	   8'h38: tmp_new_sbox2 = 8'h07;
+	   8'h39: tmp_new_sbox2 = 8'h12;
+	   8'h3a: tmp_new_sbox2 = 8'h80;
+	   8'h3b: tmp_new_sbox2 = 8'he2;
+	   8'h3c: tmp_new_sbox2 = 8'heb;
+	   8'h3d: tmp_new_sbox2 = 8'h27;
+	   8'h3e: tmp_new_sbox2 = 8'hb2;
+	   8'h3f: tmp_new_sbox2 = 8'h75;
+	   8'h40: tmp_new_sbox2 = 8'h09;
+	   8'h41: tmp_new_sbox2 = 8'h83;
+	   8'h42: tmp_new_sbox2 = 8'h2c;
+	   8'h43: tmp_new_sbox2 = 8'h1a;
+	   8'h44: tmp_new_sbox2 = 8'h1b;
+	   8'h45: tmp_new_sbox2 = 8'h6e;
+	   8'h46: tmp_new_sbox2 = 8'h5a;
+	   8'h47: tmp_new_sbox2 = 8'ha0;
+	   8'h48: tmp_new_sbox2 = 8'h52;
+	   8'h49: tmp_new_sbox2 = 8'h3b;
+	   8'h4a: tmp_new_sbox2 = 8'hd6;
+	   8'h4b: tmp_new_sbox2 = 8'hb3;
+	   8'h4c: tmp_new_sbox2 = 8'h29;
+	   8'h4d: tmp_new_sbox2 = 8'he3;
+	   8'h4e: tmp_new_sbox2 = 8'h2f;
+	   8'h4f: tmp_new_sbox2 = 8'h84;
+	   8'h50: tmp_new_sbox2 = 8'h53;
+	   8'h51: tmp_new_sbox2 = 8'hd1;
+	   8'h52: tmp_new_sbox2 = 8'h00;
+	   8'h53: tmp_new_sbox2 = 8'hed;
+	   8'h54: tmp_new_sbox2 = 8'h20;
+	   8'h55: tmp_new_sbox2 = 8'hfc;
+	   8'h56: tmp_new_sbox2 = 8'hb1;
+	   8'h57: tmp_new_sbox2 = 8'h5b;
+	   8'h58: tmp_new_sbox2 = 8'h6a;
+	   8'h59: tmp_new_sbox2 = 8'hcb;
+	   8'h5a: tmp_new_sbox2 = 8'hbe;
+	   8'h5b: tmp_new_sbox2 = 8'h39;
+	   8'h5c: tmp_new_sbox2 = 8'h4a;
+	   8'h5d: tmp_new_sbox2 = 8'h4c;
+	   8'h5e: tmp_new_sbox2 = 8'h58;
+	   8'h5f: tmp_new_sbox2 = 8'hcf;
+	   8'h60: tmp_new_sbox2 = 8'hd0;
+	   8'h61: tmp_new_sbox2 = 8'hef;
+	   8'h62: tmp_new_sbox2 = 8'haa;
+	   8'h63: tmp_new_sbox2 = 8'hfb;
+	   8'h64: tmp_new_sbox2 = 8'h43;
+	   8'h65: tmp_new_sbox2 = 8'h4d;
+	   8'h66: tmp_new_sbox2 = 8'h33;
+	   8'h67: tmp_new_sbox2 = 8'h85;
+	   8'h68: tmp_new_sbox2 = 8'h45;
+	   8'h69: tmp_new_sbox2 = 8'hf9;
+	   8'h6a: tmp_new_sbox2 = 8'h02;
+	   8'h6b: tmp_new_sbox2 = 8'h7f;
+	   8'h6c: tmp_new_sbox2 = 8'h50;
+	   8'h6d: tmp_new_sbox2 = 8'h3c;
+	   8'h6e: tmp_new_sbox2 = 8'h9f;
+	   8'h6f: tmp_new_sbox2 = 8'ha8;
+	   8'h70: tmp_new_sbox2 = 8'h51;
+	   8'h71: tmp_new_sbox2 = 8'ha3;
+	   8'h72: tmp_new_sbox2 = 8'h40;
+	   8'h73: tmp_new_sbox2 = 8'h8f;
+	   8'h74: tmp_new_sbox2 = 8'h92;
+	   8'h75: tmp_new_sbox2 = 8'h9d;
+	   8'h76: tmp_new_sbox2 = 8'h38;
+	   8'h77: tmp_new_sbox2 = 8'hf5;
+	   8'h78: tmp_new_sbox2 = 8'hbc;
+	   8'h79: tmp_new_sbox2 = 8'hb6;
+	   8'h7a: tmp_new_sbox2 = 8'hda;
+	   8'h7b: tmp_new_sbox2 = 8'h21;
+	   8'h7c: tmp_new_sbox2 = 8'h10;
+	   8'h7d: tmp_new_sbox2 = 8'hff;
+	   8'h7e: tmp_new_sbox2 = 8'hf3;
+	   8'h7f: tmp_new_sbox2 = 8'hd2;
+	   8'h80: tmp_new_sbox2 = 8'hcd;
+	   8'h81: tmp_new_sbox2 = 8'h0c;
+	   8'h82: tmp_new_sbox2 = 8'h13;
+	   8'h83: tmp_new_sbox2 = 8'hec;
+	   8'h84: tmp_new_sbox2 = 8'h5f;
+	   8'h85: tmp_new_sbox2 = 8'h97;
+	   8'h86: tmp_new_sbox2 = 8'h44;
+	   8'h87: tmp_new_sbox2 = 8'h17;
+	   8'h88: tmp_new_sbox2 = 8'hc4;
+	   8'h89: tmp_new_sbox2 = 8'ha7;
+	   8'h8a: tmp_new_sbox2 = 8'h7e;
+	   8'h8b: tmp_new_sbox2 = 8'h3d;
+	   8'h8c: tmp_new_sbox2 = 8'h64;
+	   8'h8d: tmp_new_sbox2 = 8'h5d;
+	   8'h8e: tmp_new_sbox2 = 8'h19;
+	   8'h8f: tmp_new_sbox2 = 8'h73;
+	   8'h90: tmp_new_sbox2 = 8'h60;
+	   8'h91: tmp_new_sbox2 = 8'h81;
+	   8'h92: tmp_new_sbox2 = 8'h4f;
+	   8'h93: tmp_new_sbox2 = 8'hdc;
+	   8'h94: tmp_new_sbox2 = 8'h22;
+	   8'h95: tmp_new_sbox2 = 8'h2a;
+	   8'h96: tmp_new_sbox2 = 8'h90;
+	   8'h97: tmp_new_sbox2 = 8'h88;
+	   8'h98: tmp_new_sbox2 = 8'h46;
+	   8'h99: tmp_new_sbox2 = 8'hee;
+	   8'h9a: tmp_new_sbox2 = 8'hb8;
+	   8'h9b: tmp_new_sbox2 = 8'h14;
+	   8'h9c: tmp_new_sbox2 = 8'hde;
+	   8'h9d: tmp_new_sbox2 = 8'h5e;
+	   8'h9e: tmp_new_sbox2 = 8'h0b;
+	   8'h9f: tmp_new_sbox2 = 8'hdb;
+	   8'ha0: tmp_new_sbox2 = 8'he0;
+	   8'ha1: tmp_new_sbox2 = 8'h32;
+	   8'ha2: tmp_new_sbox2 = 8'h3a;
+	   8'ha3: tmp_new_sbox2 = 8'h0a;
+	   8'ha4: tmp_new_sbox2 = 8'h49;
+	   8'ha5: tmp_new_sbox2 = 8'h06;
+	   8'ha6: tmp_new_sbox2 = 8'h24;
+	   8'ha7: tmp_new_sbox2 = 8'h5c;
+	   8'ha8: tmp_new_sbox2 = 8'hc2;
+	   8'ha9: tmp_new_sbox2 = 8'hd3;
+	   8'haa: tmp_new_sbox2 = 8'hac;
+	   8'hab: tmp_new_sbox2 = 8'h62;
+	   8'hac: tmp_new_sbox2 = 8'h91;
+	   8'had: tmp_new_sbox2 = 8'h95;
+	   8'hae: tmp_new_sbox2 = 8'he4;
+	   8'haf: tmp_new_sbox2 = 8'h79;
+	   8'hb0: tmp_new_sbox2 = 8'he7;
+	   8'hb1: tmp_new_sbox2 = 8'hc8;
+	   8'hb2: tmp_new_sbox2 = 8'h37;
+	   8'hb3: tmp_new_sbox2 = 8'h6d;
+	   8'hb4: tmp_new_sbox2 = 8'h8d;
+	   8'hb5: tmp_new_sbox2 = 8'hd5;
+	   8'hb6: tmp_new_sbox2 = 8'h4e;
+	   8'hb7: tmp_new_sbox2 = 8'ha9;
+	   8'hb8: tmp_new_sbox2 = 8'h6c;
+	   8'hb9: tmp_new_sbox2 = 8'h56;
+	   8'hba: tmp_new_sbox2 = 8'hf4;
+	   8'hbb: tmp_new_sbox2 = 8'hea;
+	   8'hbc: tmp_new_sbox2 = 8'h65;
+	   8'hbd: tmp_new_sbox2 = 8'h7a;
+	   8'hbe: tmp_new_sbox2 = 8'hae;
+	   8'hbf: tmp_new_sbox2 = 8'h08;
+	   8'hc0: tmp_new_sbox2 = 8'hba;
+	   8'hc1: tmp_new_sbox2 = 8'h78;
+	   8'hc2: tmp_new_sbox2 = 8'h25;
+	   8'hc3: tmp_new_sbox2 = 8'h2e;
+	   8'hc4: tmp_new_sbox2 = 8'h1c;
+	   8'hc5: tmp_new_sbox2 = 8'ha6;
+	   8'hc6: tmp_new_sbox2 = 8'hb4;
+	   8'hc7: tmp_new_sbox2 = 8'hc6;
+	   8'hc8: tmp_new_sbox2 = 8'he8;
+	   8'hc9: tmp_new_sbox2 = 8'hdd;
+	   8'hca: tmp_new_sbox2 = 8'h74;
+	   8'hcb: tmp_new_sbox2 = 8'h1f;
+	   8'hcc: tmp_new_sbox2 = 8'h4b;
+	   8'hcd: tmp_new_sbox2 = 8'hbd;
+	   8'hce: tmp_new_sbox2 = 8'h8b;
+	   8'hcf: tmp_new_sbox2 = 8'h8a;
+	   8'hd0: tmp_new_sbox2 = 8'h70;
+	   8'hd1: tmp_new_sbox2 = 8'h3e;
+	   8'hd2: tmp_new_sbox2 = 8'hb5;
+	   8'hd3: tmp_new_sbox2 = 8'h66;
+	   8'hd4: tmp_new_sbox2 = 8'h48;
+	   8'hd5: tmp_new_sbox2 = 8'h03;
+	   8'hd6: tmp_new_sbox2 = 8'hf6;
+	   8'hd7: tmp_new_sbox2 = 8'h0e;
+	   8'hd8: tmp_new_sbox2 = 8'h61;
+	   8'hd9: tmp_new_sbox2 = 8'h35;
+	   8'hda: tmp_new_sbox2 = 8'h57;
+	   8'hdb: tmp_new_sbox2 = 8'hb9;
+	   8'hdc: tmp_new_sbox2 = 8'h86;
+	   8'hdd: tmp_new_sbox2 = 8'hc1;
+	   8'hde: tmp_new_sbox2 = 8'h1d;
+	   8'hdf: tmp_new_sbox2 = 8'h9e;
+	   8'he0: tmp_new_sbox2 = 8'he1;
+	   8'he1: tmp_new_sbox2 = 8'hf8;
+	   8'he2: tmp_new_sbox2 = 8'h98;
+	   8'he3: tmp_new_sbox2 = 8'h11;
+	   8'he4: tmp_new_sbox2 = 8'h69;
+	   8'he5: tmp_new_sbox2 = 8'hd9;
+	   8'he6: tmp_new_sbox2 = 8'h8e;
+	   8'he7: tmp_new_sbox2 = 8'h94;
+	   8'he8: tmp_new_sbox2 = 8'h9b;
+	   8'he9: tmp_new_sbox2 = 8'h1e;
+	   8'hea: tmp_new_sbox2 = 8'h87;
+	   8'heb: tmp_new_sbox2 = 8'he9;
+	   8'hec: tmp_new_sbox2 = 8'hce;
+	   8'hed: tmp_new_sbox2 = 8'h55;
+	   8'hee: tmp_new_sbox2 = 8'h28;
+	   8'hef: tmp_new_sbox2 = 8'hdf;
+	   8'hf0: tmp_new_sbox2 = 8'h8c;
+	   8'hf1: tmp_new_sbox2 = 8'ha1;
+	   8'hf2: tmp_new_sbox2 = 8'h89;
+	   8'hf3: tmp_new_sbox2 = 8'h0d;
+	   8'hf4: tmp_new_sbox2 = 8'hbf;
+	   8'hf5: tmp_new_sbox2 = 8'he6;
+	   8'hf6: tmp_new_sbox2 = 8'h42;
+	   8'hf7: tmp_new_sbox2 = 8'h68;
+	   8'hf8: tmp_new_sbox2 = 8'h41;
+	   8'hf9: tmp_new_sbox2 = 8'h99;
+	   8'hfa: tmp_new_sbox2 = 8'h2d;
+	   8'hfb: tmp_new_sbox2 = 8'h0f;
+	   8'hfc: tmp_new_sbox2 = 8'hb0;
+	   8'hfd: tmp_new_sbox2 = 8'h54;
+	   8'hfe: tmp_new_sbox2 = 8'hbb;
+	   8'hff: tmp_new_sbox2 = 8'h16;
+      endcase // case (sboxw[15 : 8])
+    end // sbox_rom2
+
+
+  //----------------------------------------------------------------
+  // sbox_rom3
+  //
+  // The logic implemeting the ROM with mux.
+  //----------------------------------------------------------------
+  always @*
+    begin : sbox_rom3
+      case(sboxw[7 : 0])
+	   8'h00: tmp_new_sbox3 = 8'h63;
+	   8'h01: tmp_new_sbox3 = 8'h7c;
+	   8'h02: tmp_new_sbox3 = 8'h77;
+	   8'h03: tmp_new_sbox3 = 8'h7b;
+	   8'h04: tmp_new_sbox3 = 8'hf2;
+	   8'h05: tmp_new_sbox3 = 8'h6b;
+	   8'h06: tmp_new_sbox3 = 8'h6f;
+	   8'h07: tmp_new_sbox3 = 8'hc5;
+	   8'h08: tmp_new_sbox3 = 8'h30;
+	   8'h09: tmp_new_sbox3 = 8'h01;
+	   8'h0a: tmp_new_sbox3 = 8'h67;
+	   8'h0b: tmp_new_sbox3 = 8'h2b;
+	   8'h0c: tmp_new_sbox3 = 8'hfe;
+	   8'h0d: tmp_new_sbox3 = 8'hd7;
+	   8'h0e: tmp_new_sbox3 = 8'hab;
+	   8'h0f: tmp_new_sbox3 = 8'h76;
+	   8'h10: tmp_new_sbox3 = 8'hca;
+	   8'h11: tmp_new_sbox3 = 8'h82;
+	   8'h12: tmp_new_sbox3 = 8'hc9;
+	   8'h13: tmp_new_sbox3 = 8'h7d;
+	   8'h14: tmp_new_sbox3 = 8'hfa;
+	   8'h15: tmp_new_sbox3 = 8'h59;
+	   8'h16: tmp_new_sbox3 = 8'h47;
+	   8'h17: tmp_new_sbox3 = 8'hf0;
+	   8'h18: tmp_new_sbox3 = 8'had;
+	   8'h19: tmp_new_sbox3 = 8'hd4;
+	   8'h1a: tmp_new_sbox3 = 8'ha2;
+	   8'h1b: tmp_new_sbox3 = 8'haf;
+	   8'h1c: tmp_new_sbox3 = 8'h9c;
+	   8'h1d: tmp_new_sbox3 = 8'ha4;
+	   8'h1e: tmp_new_sbox3 = 8'h72;
+	   8'h1f: tmp_new_sbox3 = 8'hc0;
+	   8'h20: tmp_new_sbox3 = 8'hb7;
+	   8'h21: tmp_new_sbox3 = 8'hfd;
+	   8'h22: tmp_new_sbox3 = 8'h93;
+	   8'h23: tmp_new_sbox3 = 8'h26;
+	   8'h24: tmp_new_sbox3 = 8'h36;
+	   8'h25: tmp_new_sbox3 = 8'h3f;
+	   8'h26: tmp_new_sbox3 = 8'hf7;
+	   8'h27: tmp_new_sbox3 = 8'hcc;
+	   8'h28: tmp_new_sbox3 = 8'h34;
+	   8'h29: tmp_new_sbox3 = 8'ha5;
+	   8'h2a: tmp_new_sbox3 = 8'he5;
+	   8'h2b: tmp_new_sbox3 = 8'hf1;
+	   8'h2c: tmp_new_sbox3 = 8'h71;
+	   8'h2d: tmp_new_sbox3 = 8'hd8;
+	   8'h2e: tmp_new_sbox3 = 8'h31;
+	   8'h2f: tmp_new_sbox3 = 8'h15;
+	   8'h30: tmp_new_sbox3 = 8'h04;
+	   8'h31: tmp_new_sbox3 = 8'hc7;
+	   8'h32: tmp_new_sbox3 = 8'h23;
+	   8'h33: tmp_new_sbox3 = 8'hc3;
+	   8'h34: tmp_new_sbox3 = 8'h18;
+	   8'h35: tmp_new_sbox3 = 8'h96;
+	   8'h36: tmp_new_sbox3 = 8'h05;
+	   8'h37: tmp_new_sbox3 = 8'h9a;
+	   8'h38: tmp_new_sbox3 = 8'h07;
+	   8'h39: tmp_new_sbox3 = 8'h12;
+	   8'h3a: tmp_new_sbox3 = 8'h80;
+	   8'h3b: tmp_new_sbox3 = 8'he2;
+	   8'h3c: tmp_new_sbox3 = 8'heb;
+	   8'h3d: tmp_new_sbox3 = 8'h27;
+	   8'h3e: tmp_new_sbox3 = 8'hb2;
+	   8'h3f: tmp_new_sbox3 = 8'h75;
+	   8'h40: tmp_new_sbox3 = 8'h09;
+	   8'h41: tmp_new_sbox3 = 8'h83;
+	   8'h42: tmp_new_sbox3 = 8'h2c;
+	   8'h43: tmp_new_sbox3 = 8'h1a;
+	   8'h44: tmp_new_sbox3 = 8'h1b;
+	   8'h45: tmp_new_sbox3 = 8'h6e;
+	   8'h46: tmp_new_sbox3 = 8'h5a;
+	   8'h47: tmp_new_sbox3 = 8'ha0;
+	   8'h48: tmp_new_sbox3 = 8'h52;
+	   8'h49: tmp_new_sbox3 = 8'h3b;
+	   8'h4a: tmp_new_sbox3 = 8'hd6;
+	   8'h4b: tmp_new_sbox3 = 8'hb3;
+	   8'h4c: tmp_new_sbox3 = 8'h29;
+	   8'h4d: tmp_new_sbox3 = 8'he3;
+	   8'h4e: tmp_new_sbox3 = 8'h2f;
+	   8'h4f: tmp_new_sbox3 = 8'h84;
+	   8'h50: tmp_new_sbox3 = 8'h53;
+	   8'h51: tmp_new_sbox3 = 8'hd1;
+	   8'h52: tmp_new_sbox3 = 8'h00;
+	   8'h53: tmp_new_sbox3 = 8'hed;
+	   8'h54: tmp_new_sbox3 = 8'h20;
+	   8'h55: tmp_new_sbox3 = 8'hfc;
+	   8'h56: tmp_new_sbox3 = 8'hb1;
+	   8'h57: tmp_new_sbox3 = 8'h5b;
+	   8'h58: tmp_new_sbox3 = 8'h6a;
+	   8'h59: tmp_new_sbox3 = 8'hcb;
+	   8'h5a: tmp_new_sbox3 = 8'hbe;
+	   8'h5b: tmp_new_sbox3 = 8'h39;
+	   8'h5c: tmp_new_sbox3 = 8'h4a;
+	   8'h5d: tmp_new_sbox3 = 8'h4c;
+	   8'h5e: tmp_new_sbox3 = 8'h58;
+	   8'h5f: tmp_new_sbox3 = 8'hcf;
+	   8'h60: tmp_new_sbox3 = 8'hd0;
+	   8'h61: tmp_new_sbox3 = 8'hef;
+	   8'h62: tmp_new_sbox3 = 8'haa;
+	   8'h63: tmp_new_sbox3 = 8'hfb;
+	   8'h64: tmp_new_sbox3 = 8'h43;
+	   8'h65: tmp_new_sbox3 = 8'h4d;
+	   8'h66: tmp_new_sbox3 = 8'h33;
+	   8'h67: tmp_new_sbox3 = 8'h85;
+	   8'h68: tmp_new_sbox3 = 8'h45;
+	   8'h69: tmp_new_sbox3 = 8'hf9;
+	   8'h6a: tmp_new_sbox3 = 8'h02;
+	   8'h6b: tmp_new_sbox3 = 8'h7f;
+	   8'h6c: tmp_new_sbox3 = 8'h50;
+	   8'h6d: tmp_new_sbox3 = 8'h3c;
+	   8'h6e: tmp_new_sbox3 = 8'h9f;
+	   8'h6f: tmp_new_sbox3 = 8'ha8;
+	   8'h70: tmp_new_sbox3 = 8'h51;
+	   8'h71: tmp_new_sbox3 = 8'ha3;
+	   8'h72: tmp_new_sbox3 = 8'h40;
+	   8'h73: tmp_new_sbox3 = 8'h8f;
+	   8'h74: tmp_new_sbox3 = 8'h92;
+	   8'h75: tmp_new_sbox3 = 8'h9d;
+	   8'h76: tmp_new_sbox3 = 8'h38;
+	   8'h77: tmp_new_sbox3 = 8'hf5;
+	   8'h78: tmp_new_sbox3 = 8'hbc;
+	   8'h79: tmp_new_sbox3 = 8'hb6;
+	   8'h7a: tmp_new_sbox3 = 8'hda;
+	   8'h7b: tmp_new_sbox3 = 8'h21;
+	   8'h7c: tmp_new_sbox3 = 8'h10;
+	   8'h7d: tmp_new_sbox3 = 8'hff;
+	   8'h7e: tmp_new_sbox3 = 8'hf3;
+	   8'h7f: tmp_new_sbox3 = 8'hd2;
+	   8'h80: tmp_new_sbox3 = 8'hcd;
+	   8'h81: tmp_new_sbox3 = 8'h0c;
+	   8'h82: tmp_new_sbox3 = 8'h13;
+	   8'h83: tmp_new_sbox3 = 8'hec;
+	   8'h84: tmp_new_sbox3 = 8'h5f;
+	   8'h85: tmp_new_sbox3 = 8'h97;
+	   8'h86: tmp_new_sbox3 = 8'h44;
+	   8'h87: tmp_new_sbox3 = 8'h17;
+	   8'h88: tmp_new_sbox3 = 8'hc4;
+	   8'h89: tmp_new_sbox3 = 8'ha7;
+	   8'h8a: tmp_new_sbox3 = 8'h7e;
+	   8'h8b: tmp_new_sbox3 = 8'h3d;
+	   8'h8c: tmp_new_sbox3 = 8'h64;
+	   8'h8d: tmp_new_sbox3 = 8'h5d;
+	   8'h8e: tmp_new_sbox3 = 8'h19;
+	   8'h8f: tmp_new_sbox3 = 8'h73;
+	   8'h90: tmp_new_sbox3 = 8'h60;
+	   8'h91: tmp_new_sbox3 = 8'h81;
+	   8'h92: tmp_new_sbox3 = 8'h4f;
+	   8'h93: tmp_new_sbox3 = 8'hdc;
+	   8'h94: tmp_new_sbox3 = 8'h22;
+	   8'h95: tmp_new_sbox3 = 8'h2a;
+	   8'h96: tmp_new_sbox3 = 8'h90;
+	   8'h97: tmp_new_sbox3 = 8'h88;
+	   8'h98: tmp_new_sbox3 = 8'h46;
+	   8'h99: tmp_new_sbox3 = 8'hee;
+	   8'h9a: tmp_new_sbox3 = 8'hb8;
+	   8'h9b: tmp_new_sbox3 = 8'h14;
+	   8'h9c: tmp_new_sbox3 = 8'hde;
+	   8'h9d: tmp_new_sbox3 = 8'h5e;
+	   8'h9e: tmp_new_sbox3 = 8'h0b;
+	   8'h9f: tmp_new_sbox3 = 8'hdb;
+	   8'ha0: tmp_new_sbox3 = 8'he0;
+	   8'ha1: tmp_new_sbox3 = 8'h32;
+	   8'ha2: tmp_new_sbox3 = 8'h3a;
+	   8'ha3: tmp_new_sbox3 = 8'h0a;
+	   8'ha4: tmp_new_sbox3 = 8'h49;
+	   8'ha5: tmp_new_sbox3 = 8'h06;
+	   8'ha6: tmp_new_sbox3 = 8'h24;
+	   8'ha7: tmp_new_sbox3 = 8'h5c;
+	   8'ha8: tmp_new_sbox3 = 8'hc2;
+	   8'ha9: tmp_new_sbox3 = 8'hd3;
+	   8'haa: tmp_new_sbox3 = 8'hac;
+	   8'hab: tmp_new_sbox3 = 8'h62;
+	   8'hac: tmp_new_sbox3 = 8'h91;
+	   8'had: tmp_new_sbox3 = 8'h95;
+	   8'hae: tmp_new_sbox3 = 8'he4;
+	   8'haf: tmp_new_sbox3 = 8'h79;
+	   8'hb0: tmp_new_sbox3 = 8'he7;
+	   8'hb1: tmp_new_sbox3 = 8'hc8;
+	   8'hb2: tmp_new_sbox3 = 8'h37;
+	   8'hb3: tmp_new_sbox3 = 8'h6d;
+	   8'hb4: tmp_new_sbox3 = 8'h8d;
+	   8'hb5: tmp_new_sbox3 = 8'hd5;
+	   8'hb6: tmp_new_sbox3 = 8'h4e;
+	   8'hb7: tmp_new_sbox3 = 8'ha9;
+	   8'hb8: tmp_new_sbox3 = 8'h6c;
+	   8'hb9: tmp_new_sbox3 = 8'h56;
+	   8'hba: tmp_new_sbox3 = 8'hf4;
+	   8'hbb: tmp_new_sbox3 = 8'hea;
+	   8'hbc: tmp_new_sbox3 = 8'h65;
+	   8'hbd: tmp_new_sbox3 = 8'h7a;
+	   8'hbe: tmp_new_sbox3 = 8'hae;
+	   8'hbf: tmp_new_sbox3 = 8'h08;
+	   8'hc0: tmp_new_sbox3 = 8'hba;
+	   8'hc1: tmp_new_sbox3 = 8'h78;
+	   8'hc2: tmp_new_sbox3 = 8'h25;
+	   8'hc3: tmp_new_sbox3 = 8'h2e;
+	   8'hc4: tmp_new_sbox3 = 8'h1c;
+	   8'hc5: tmp_new_sbox3 = 8'ha6;
+	   8'hc6: tmp_new_sbox3 = 8'hb4;
+	   8'hc7: tmp_new_sbox3 = 8'hc6;
+	   8'hc8: tmp_new_sbox3 = 8'he8;
+	   8'hc9: tmp_new_sbox3 = 8'hdd;
+	   8'hca: tmp_new_sbox3 = 8'h74;
+	   8'hcb: tmp_new_sbox3 = 8'h1f;
+	   8'hcc: tmp_new_sbox3 = 8'h4b;
+	   8'hcd: tmp_new_sbox3 = 8'hbd;
+	   8'hce: tmp_new_sbox3 = 8'h8b;
+	   8'hcf: tmp_new_sbox3 = 8'h8a;
+	   8'hd0: tmp_new_sbox3 = 8'h70;
+	   8'hd1: tmp_new_sbox3 = 8'h3e;
+	   8'hd2: tmp_new_sbox3 = 8'hb5;
+	   8'hd3: tmp_new_sbox3 = 8'h66;
+	   8'hd4: tmp_new_sbox3 = 8'h48;
+	   8'hd5: tmp_new_sbox3 = 8'h03;
+	   8'hd6: tmp_new_sbox3 = 8'hf6;
+	   8'hd7: tmp_new_sbox3 = 8'h0e;
+	   8'hd8: tmp_new_sbox3 = 8'h61;
+	   8'hd9: tmp_new_sbox3 = 8'h35;
+	   8'hda: tmp_new_sbox3 = 8'h57;
+	   8'hdb: tmp_new_sbox3 = 8'hb9;
+	   8'hdc: tmp_new_sbox3 = 8'h86;
+	   8'hdd: tmp_new_sbox3 = 8'hc1;
+	   8'hde: tmp_new_sbox3 = 8'h1d;
+	   8'hdf: tmp_new_sbox3 = 8'h9e;
+	   8'he0: tmp_new_sbox3 = 8'he1;
+	   8'he1: tmp_new_sbox3 = 8'hf8;
+	   8'he2: tmp_new_sbox3 = 8'h98;
+	   8'he3: tmp_new_sbox3 = 8'h11;
+	   8'he4: tmp_new_sbox3 = 8'h69;
+	   8'he5: tmp_new_sbox3 = 8'hd9;
+	   8'he6: tmp_new_sbox3 = 8'h8e;
+	   8'he7: tmp_new_sbox3 = 8'h94;
+	   8'he8: tmp_new_sbox3 = 8'h9b;
+	   8'he9: tmp_new_sbox3 = 8'h1e;
+	   8'hea: tmp_new_sbox3 = 8'h87;
+	   8'heb: tmp_new_sbox3 = 8'he9;
+	   8'hec: tmp_new_sbox3 = 8'hce;
+	   8'hed: tmp_new_sbox3 = 8'h55;
+	   8'hee: tmp_new_sbox3 = 8'h28;
+	   8'hef: tmp_new_sbox3 = 8'hdf;
+	   8'hf0: tmp_new_sbox3 = 8'h8c;
+	   8'hf1: tmp_new_sbox3 = 8'ha1;
+	   8'hf2: tmp_new_sbox3 = 8'h89;
+	   8'hf3: tmp_new_sbox3 = 8'h0d;
+	   8'hf4: tmp_new_sbox3 = 8'hbf;
+	   8'hf5: tmp_new_sbox3 = 8'he6;
+	   8'hf6: tmp_new_sbox3 = 8'h42;
+	   8'hf7: tmp_new_sbox3 = 8'h68;
+	   8'hf8: tmp_new_sbox3 = 8'h41;
+	   8'hf9: tmp_new_sbox3 = 8'h99;
+	   8'hfa: tmp_new_sbox3 = 8'h2d;
+	   8'hfb: tmp_new_sbox3 = 8'h0f;
+	   8'hfc: tmp_new_sbox3 = 8'hb0;
+	   8'hfd: tmp_new_sbox3 = 8'h54;
+	   8'hfe: tmp_new_sbox3 = 8'hbb;
+	   8'hff: tmp_new_sbox3 = 8'h16;
+      endcase // case (sboxw[7 : 0])
+    end // sbox_rom3
+
+endmodule // aes_sbox
+
+//======================================================================
+// EOF aes_sbox.v
+//======================================================================
author	Joachim Strömbergson <joachim@secworks.se>	2014-11-27 15:48:42 +0100
committer	Joachim Strömbergson <joachim@secworks.se>	2014-11-27 15:48:42 +0100
commit	1ecc3b5ccceda62110c20c55683167ce9ab3cf99 (patch)
tree	bd3301e4e9ca0bf49e9bd521502700430a514511
parent	be15776087991ae3f2f7874f67c79256c11016aa (diff)