Adding support for linting the AES core.

1 files changed, 6 insertions, 0 deletions

diff --git a/toolruns/Makefile b/toolruns/Makefile
index 105524e..835a92f 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -52,6 +52,7 @@ TB_ENCIPHER_SRC =../src/tb/tb_aes_encipher_block.v
 TB_DECIPHER_SRC =../src/tb/tb_aes_decipher_block.v
 
 CC=iverilog
+LINT=verilator
 
 
 all: top.sim core.sim keymem.sim encipher.sim decipher.sim
@@ -96,6 +97,10 @@ sim-top: top.sim
 	./top.sim
 
 
+lint:
+	verilator +1364-2001ext+ --lint-only -Wall $(TOP_SRC)
+
+
 clean:
 	rm -f decipher.sim
 	rm -f encipher.sim
@@ -110,6 +115,7 @@ help:
 	@echo "Supported targets:"
 	@echo "------------------"
 	@echo "all:          Build all simulation targets."
+	@echo "lint:         Lint all rtl source files."
 	@echo "top.sim:      Build top level simulation target."
 	@echo "core.sim:     Build core level simulation target."
 	@echo "keymem.sim:   Build key memory simulation target."