Added missing implementation results for Xilinx Artix7.

1 files changed, 8 insertions, 0 deletions

diff --git a/README.md b/README.md
index f8a04fc..1b00442 100644
--- a/README.md
+++ b/README.md
@@ -30,6 +30,7 @@ of cycles to two cycles for each round.
 ## Implementation results ##
 The core has been implemented in Altera and Xilinx FPGA devices.
 
+
 ### Altera Cyclone IV GX ###
 - 7497 LEs
 - 2994 Regs
@@ -51,3 +52,10 @@ Removing the decipher module yields:
 - 3000 regs
 - 100 MHz
 - 5 cycles/round
+
+
+### Xilinx Artix7-3 T200 ###
+- 2102 slices
+- 2991 regs
+- 113 MHz (8.79ns)
+- 5 cycles/round