From 83d7c243f4f1b31bf619f4b47634a866a6a1d346 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Tue, 22 May 2018 13:17:47 +0200
Subject: Added missing implementation results for Xilinx Artix7.

---
 README.md | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/README.md b/README.md
index f8a04fc..1b00442 100644
--- a/README.md
+++ b/README.md
@@ -30,6 +30,7 @@ of cycles to two cycles for each round.
 ## Implementation results ##
 The core has been implemented in Altera and Xilinx FPGA devices.
 
+
 ### Altera Cyclone IV GX ###
 - 7497 LEs
 - 2994 Regs
@@ -51,3 +52,10 @@ Removing the decipher module yields:
 - 3000 regs
 - 100 MHz
 - 5 cycles/round
+
+
+### Xilinx Artix7-3 T200 ###
+- 2102 slices
+- 2991 regs
+- 113 MHz (8.79ns)
+- 5 cycles/round
-- 
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