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<h1>vndecorrelator</h1>
<p>A Verilog implementation of a von Neumann decorrelator.</p>
<p>This tiny module consumes pairs of bits and generates decorrelated
bits. Basically given a sequence of two bits, the decorrelator will:</p>
<p>0, 1: Emit 1
1, 0: Emit 0
0, 0: Emit nothing
1, 1: Emit nothing</p>
<p>The rate of bits emitted is thus at most half of the bitrate on the
input.</p>
<p>The module is synchronous, but bits may arrive a number of cycles
between eachother. The module will set the syn_out flag during one cycle
to signal that the value in data_out is a valid bit.</p>
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