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authorRob Austein <sra@hactrn.net>2020-09-13 23:04:30 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:04:30 +0000
commitb092ffbcbe2c9398494f7dc9db6f0796971633e0 (patch)
tree6fabf690f1ebf485a9fea9af5298e44ad2a59a3e /raw-wiki-dump/GitRepositories%2Fcore%2Frng%2Fvndecorrelator
parent9d927e49d9c10fc16c6dfa4a2a96cdb6216e4e2b (diff)
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+{{{
+#!htmlcomment
+
+This page is maintained automatically by a script. Don't modify this page by hand,
+your changes will just be overwritten the next time the script runs. Talk to your
+Friendly Neighborhood Repository Maintainer if you need to change something here.
+
+}}}
+
+{{{
+#!html
+<h1>vndecorrelator</h1>
+
+<p>A Verilog implementation of a von Neumann decorrelator.</p>
+
+<p>This tiny module consumes pairs of bits and generates decorrelated
+bits. Basically given a sequence of two bits, the decorrelator will:</p>
+
+<p>0, 1: Emit 1
+1, 0: Emit 0
+0, 0: Emit nothing
+1, 1: Emit nothing</p>
+
+<p>The rate of bits emitted is thus at most half of the bitrate on the
+input.</p>
+
+<p>The module is synchronous, but bits may arrive a number of cycles
+between eachother. The module will set the syn_out flag during one cycle
+to signal that the value in data_out is a valid bit.</p>
+}}}
+
+[[RepositoryIndex(format=table,glob=core/rng/vndecorrelator)]]
+
+|| Clone `https://git.cryptech.is/core/rng/vndecorrelator.git` ||