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authorRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
commit891730d13b324fad916572a82f0bd610c5de9aad (patch)
treef46c94ddfff34f15aafe7cac0596716d1c13c412 /raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g
parentb092ffbcbe2c9398494f7dc9db6f0796971633e0 (diff)
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-{{{
-#!htmlcomment
-
-This page is maintained automatically by a script. Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs. Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-}}}
-
-{{{
-#!html
-<h1>platform/terasic_c5g</h1>
-
-<p>Platform-specific files for the TerasIC C5G development board.</p>
-
-<h2>Introduction</h2>
-
-<p>This includes the Verilog top-level files and build systems for Terasic
-with a UART interface.</p>
-
-<h2>Status</h2>
-
-<p><strong><em>(2015-03-16)</em></strong>
-Reorganized. Built using Altera Quarus 14.1.</p>
-
-<p><strong><em>(2014-03-07)</em></strong>
-Initial version. Build using Altera Quarus 13.1.</p>
-
-<ul>
-<li>Cyclone 5 GX device</li>
-<li>2847 ALMs and</li>
-<li>3665 registers</li>
-<li>86 MHz</li>
-</ul>
-}}}
-
-[[RepositoryIndex(format=table,glob=core/platform/terasic_c5g)]]
-
-|| Clone `https://git.cryptech.is/core/platform/terasic_c5g.git` ||