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<h1>platform/terasic_c5g</h1>
<p>Platform-specific files for the TerasIC C5G development board.</p>
<h2>Introduction</h2>
<p>This includes the Verilog top-level files and build systems for Terasic
with a UART interface.</p>
<h2>Status</h2>
<p><strong><em>(2015-03-16)</em></strong>
Reorganized. Built using Altera Quarus 14.1.</p>
<p><strong><em>(2014-03-07)</em></strong>
Initial version. Build using Altera Quarus 13.1.</p>
<ul>
<li>Cyclone 5 GX device</li>
<li>2847 ALMs and</li>
<li>3665 registers</li>
<li>86 MHz</li>
</ul>
}}}
[[RepositoryIndex(format=table,glob=core/platform/terasic_c5g)]]
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