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| author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
| commit | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (patch) | |
| tree | ca300cbdbc9b1ca3224441e50375d94c092223e8 /raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md | |
| parent | 4ba5e00d5cdd42087a76e379cc39604b2da89ea4 (diff) | |
Initial conversion pass
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md')
| -rw-r--r-- | raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md new file mode 100644 index 0000000..fb1551c --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Feim.md @@ -0,0 +1,21 @@ +``` +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +``` + +``` +#!html +<h1>eim</h1> + +<p>Verilog implementation of the eim interface used to connect FPGA cores +to the Freescale i.MX6 CPU.</p> +``` + +[[RepositoryIndex(format=table,glob=core/comm/eim)]] + +| Clone `https://git.cryptech.is/core/comm/eim.git` | +|---| |