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| author | Rob Austein <sra@hactrn.net> | 2021-05-09 23:45:48 +0000 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2021-05-09 23:45:48 +0000 |
| commit | 78b3ed35c726cf8ef0ec4c4e7753e6f4775b9001 (patch) | |
| tree | c0807af26f39d382e0472ed9cef26322d3b1b56a /pelican/content/RoughV1.md | |
| parent | 96f8ab4641056020192175c0a02c562e8113dbd7 (diff) | |
Finally get hanging text in lists mostly right
Diffstat (limited to 'pelican/content/RoughV1.md')
| -rw-r--r-- | pelican/content/RoughV1.md | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md index b52a3cf..c6bb597 100644 --- a/pelican/content/RoughV1.md +++ b/pelican/content/RoughV1.md @@ -121,11 +121,9 @@ Verilog. * What components we ship - life is compromise * Toolchains, Verilog, C, ... * FPGAs and ASICs use a Verilog-based toolchain. There are no mature open - Verilog compilers so the [DDC approach](http://www.dwheeler.com/trusting-trust/) will not work. Net-list optimization is also an issue. We're looking into this, but it's going to be really hard. Research for v2. - * Protoyping platform * [Bunnie's Novena laptop](http://www.bunniestudios.com/blog/?p=3265) * Altera Evaluation Board |