Even more links

15 files changed, 34 insertions, 28 deletions

diff --git a/pelican/content/AlphaBoardStrategy.md b/pelican/content/AlphaBoardStrategy.md
index f83d7dd..b6b07ae 100644
--- a/pelican/content/AlphaBoardStrategy.md
+++ b/pelican/content/AlphaBoardStrategy.md
@@ -8,8 +8,8 @@ Develop a first, custom HSM board that can be used to support a first set of app
 
 
 * The use cases and requirements for the alpha board are specified on the [Dashboard](http://trac.cryptech.is/wiki/Dashboard).
-* The basic blocks of the Alpha board is [wiki:Hardware "shown here"].
-* The [wiki:AlphaBoardComponents "BOM and component requirements"].
+* The basic blocks of the Alpha board is ["shown here"](Hardware).
+* The ["BOM and component requirements"](AlphaBoardComponents).
 * The detailed ["Alpha board functional drawing"](http://trac.cryptech.is/browser/doc/design/Alpha_board_drawing.pdf).
 
 
@@ -17,7 +17,7 @@ Develop a first, custom HSM board that can be used to support a first set of app
 ## Plan
 1. Choose FPGA and ARM (done)
 2. Develop BOM, requirements and functional diagram (done-ish).
-3. Develop complete [wiki:AlphaSchematics "schematics"] (almost done).
+3. Develop complete ["schematics"](AlphaSchematics) (almost done).
 4. Develop dev-board ouorselves to connect chosen ARM to FPGA on Novena, to do some early development and testing in parallell with step 5.
 5. Get professional designer to do many-layer PCB from schematics.
 6. Manufacture a couple of boards (~10).
diff --git a/pelican/content/AlphaSchematics.md b/pelican/content/AlphaSchematics.md
index f1b0ca9..40dad8a 100644
--- a/pelican/content/AlphaSchematics.md
+++ b/pelican/content/AlphaSchematics.md
@@ -9,4 +9,4 @@ PDF and Eagle files available for download here in the [[source:/hardware/eagle/
 
 The schematics are based on the dev-bridge board that we made in the summer of 2015, which is why it is called rev02.
 
-We are currently seeking review of the schematics to finalize them before starting layout. A log of various peoples review comments is kept [wiki:AlphaReviewLog here].
+We are currently seeking review of the schematics to finalize them before starting layout. A log of various peoples review comments is kept [here](AlphaReviewLog).
diff --git a/pelican/content/DNSSEC.md b/pelican/content/DNSSEC.md
index a95f61a..4b1ac47 100644
--- a/pelican/content/DNSSEC.md
+++ b/pelican/content/DNSSEC.md
@@ -4,4 +4,4 @@ Date: 2016-12-15 22:43
 # DNSSEC
 
 
-- [wiki:DNSSEC/Requirements DNSSEC Requirements]
+- [DNSSEC Requirements](DNSSEC/Requirements)
diff --git a/pelican/content/DevBridgeBoard.md b/pelican/content/DevBridgeBoard.md
index efef738..ef0c258 100644
--- a/pelican/content/DevBridgeBoard.md
+++ b/pelican/content/DevBridgeBoard.md
@@ -41,4 +41,4 @@ you want to avoid scraping them with the bolt head or the nut. I happen to
 be using a countersink-head bolt, which is beveled toward the shaft, but
 it's probably even better to use a nylon washer.
 
-All the software, as well as flashing instructions, are at [wiki:GitRepositories/sw/stm32].
+All the software, as well as flashing instructions, are at [GitRepositories/sw/stm32](GitRepositories/sw/stm32).
diff --git a/pelican/content/DisasterRecovery.md b/pelican/content/DisasterRecovery.md
index 08bfd6f..51ca05c 100644
--- a/pelican/content/DisasterRecovery.md
+++ b/pelican/content/DisasterRecovery.md
@@ -32,7 +32,7 @@ best case scenario. Log in as wheel with the default PIN
 able to reset the PINs.
 
 If you forgot the PIN, I feel sorry for you. The only way out of this is
-via [wiki:UsingSTLink ST-LINK]. The easiest way is to debug with `gdb`, set a breakpoint on
+via [ST-LINK](UsingSTLink). The easiest way is to debug with `gdb`, set a breakpoint on
 `hal_rpc_login`, and issue the gdb command `return 0`.
 
 ## Oh no, I forgot (or reset) the master key
diff --git a/pelican/content/ExternalProjects.md b/pelican/content/ExternalProjects.md
index a2a790a..b5ea421 100644
--- a/pelican/content/ExternalProjects.md
+++ b/pelican/content/ExternalProjects.md
@@ -5,4 +5,4 @@ Modified: 2018-09-17 10:27
 External projects using [CrypTech](https://cryptech.is/) technology.
 
 
-* [wiki:ExternalProjectsTorHSM TorHSM]
+* [TorHSM](ExternalProjectsTorHSM)
diff --git a/pelican/content/Hardware.md b/pelican/content/Hardware.md
index 19c278b..4fc2d99 100644
--- a/pelican/content/Hardware.md
+++ b/pelican/content/Hardware.md
@@ -9,7 +9,7 @@ Various generic FPGA development boards.
 
 ## Generation 2
 
-//[wiki:CoretestHashesNovena Novena]//
+//[Novena](CoretestHashesNovena)//
 
 ## Generation 3
 
@@ -28,4 +28,4 @@ For the ARM, we think we want
     * All components must be free of any GPL-like virus or restrictions
 
 
-[wiki:AlphaBoardComponents The BOM and board requirements for the alpha board].
+[The BOM and board requirements for the alpha board](AlphaBoardComponents).
diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md
index 72dc28f..ac91cf2 100644
--- a/pelican/content/OpenCryptoChip.md
+++ b/pelican/content/OpenCryptoChip.md
@@ -68,7 +68,7 @@ We need to support key wrapping. Some pointers:
 
 
 # Rough Cut at v0.01 Proof of Concept Feature Set
-As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a [wiki:RoughV1 proposed version 0.01 product] as a proof of concept and a demonstration of the project tools, team, and architecture
+As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a [proposed version 0.01 product](RoughV1) as a proof of concept and a demonstration of the project tools, team, and architecture
   
 
   
@@ -91,10 +91,10 @@ As a proof of concept, to validate as much as possible the assurance of the tool
 
 # Ongoing Development
 
-* [wiki:SunetInitialDevelopment "SUNET is sponsoring the first two development steps"] currently being done.
-* [wiki:TRNGDevelopment " Investigation and planning of a TRNG with entropy sources"]
-* [wiki:EDAToolchainSurvey" Investigation of possible EDA tools and ways to do open and assured HW development"]
-* [wiki:SideChannel" Collection about side-channel attacks and detection, mitigation methods"]
+* ["SUNET is sponsoring the first two development steps"](SunetInitialDevelopment) currently being done.
+* [" Investigation and planning of a TRNG with entropy sources"](TRNGDevelopment)
+* [Investigation of possible EDA tools and ways to do open and assured HW development"](EDAToolchainSurvey")
+* [Collection about side-channel attacks and detection, mitigation methods"](SideChannel")
 
 
 # v0.1 Major Sub-Projects
@@ -114,7 +114,7 @@ As a proof of concept, to validate as much as possible the assurance of the tool
 * TerasIC C5G Cyclone 5 GX Starter Kit. Includes an Altera C5GX FPGA. This board is used for core, subsystem development and verification. Info, documentation and ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830
 
 
-Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hashes on the C5G board"].
+Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](CoretestHashesC5G).
 
 
 * TerasIC DE0-Nano board. This tiny, USB powered board is used for core development and verification. Info, documentation, resources, ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593
@@ -128,7 +128,7 @@ Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hash
 
 * Research
 * Select
-* [wiki:InterconnectStandards "On-chip Interconnect Standards"] to use.
+* ["On-chip Interconnect Standards"](InterconnectStandards) to use.
 
 
 ## Methods and Validation
@@ -190,4 +190,4 @@ Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hash
 
 
 # Future Development
-The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible [wiki:ASICImplementations "ASIC Implementations"].
+The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible ["ASIC Implementations"](ASICImplementations).
diff --git a/pelican/content/OpenDNSSEC.md b/pelican/content/OpenDNSSEC.md
index 6c27410..39698f1 100644
--- a/pelican/content/OpenDNSSEC.md
+++ b/pelican/content/OpenDNSSEC.md
@@ -16,7 +16,7 @@ Modified: 2017-05-13 21:34
 apt-get install cryptech-alpha opendnssec opensc
 ```
 
-Once you have the software package installed, you may need to [wiki:Upgrading upgrade your HSM's firmware].
+Once you have the software package installed, you may need to [upgrade your HSM's firmware](Upgrading).
 
 ## Configure the HSM
 
diff --git a/pelican/content/ProjectArchive.md b/pelican/content/ProjectArchive.md
index 2ceb6d3..b13e8b9 100644
--- a/pelican/content/ProjectArchive.md
+++ b/pelican/content/ProjectArchive.md
@@ -4,4 +4,4 @@ Date: 2016-12-15 22:44
 *Page Under Construction*
 
 # Project Archive and Far Future Planning
-## [wiki:AssuredTooChain Assured Tool Chain]
+## [Assured Tool Chain](AssuredTooChain)
diff --git a/pelican/content/ProjectStatus.md b/pelican/content/ProjectStatus.md
index fb59d88..3130c73 100644
--- a/pelican/content/ProjectStatus.md
+++ b/pelican/content/ProjectStatus.md
@@ -5,7 +5,7 @@ Date: 2016-12-15 22:44
 
 # Project Status
 
-## [wiki:Dashboard Project Dashboard]
+## [Project Dashboard](Dashboard)
 
 ## Crypto Chip Design and Prototype
 
@@ -19,4 +19,4 @@ Date: 2016-12-15 22:44
 
 ## Pilot Project
 
-* [wiki:DNSSEC Requirements]
+* [Requirements](DNSSEC)
diff --git a/pelican/content/QuickStart.md b/pelican/content/QuickStart.md
index f2cee63..bb2d982 100644
--- a/pelican/content/QuickStart.md
+++ b/pelican/content/QuickStart.md
@@ -23,7 +23,7 @@ The current hardware is the AlphaBoard.  More information (to be organized at so
 * AlphaSchematics
 
 
-The Alpha board currently ships with very old firmware, but you can [wiki:Upgrading upgrade it yourself].
+The Alpha board currently ships with very old firmware, but you can [upgrade it yourself](Upgrading).
 
 # DNSSEC signing using OpenDNSSEC
 
diff --git a/pelican/content/ReleaseNotes.md b/pelican/content/ReleaseNotes.md
index f352098..8db8024 100644
--- a/pelican/content/ReleaseNotes.md
+++ b/pelican/content/ReleaseNotes.md
@@ -27,8 +27,8 @@ Modified: 2017-05-13 19:18
 Getting started with 3.0:
 
 
-* [wiki:BinaryPackages Install the software].
-* [wiki:Upgrading Upgrade the firmware].  **Please note the warnings about bricking your HSM**, how to avoid that, and what to do if you failed to avoid it.
+* [Install the software](BinaryPackages).
+* [Upgrade the firmware](Upgrading).  **Please note the warnings about bricking your HSM**, how to avoid that, and what to do if you failed to avoid it.
 * Set the usual environment variables, perhaps using `cryptech_probe`.
 * Start the multiplexer daemon `cryptech_muxd`.
 
diff --git a/pelican/content/UpgradeToKSNG.md b/pelican/content/UpgradeToKSNG.md
index 186c6e9..99b88ed 100644
--- a/pelican/content/UpgradeToKSNG.md
+++ b/pelican/content/UpgradeToKSNG.md
@@ -161,7 +161,7 @@ cryptech> masterkey set
 
 If the above procedure somehow goes horribly wrong and bricks your
 alpha, you can still recover, but you'll need an ST-LINK programmer.
-There's some discussion of this at [[wiki:GitRepositories/sw/stm32]].
+There's some discussion of this at [[GitRepositories/sw/stm32]](GitRepositories/sw/stm32]).
 
 Possible sources for the ST-LINK programmer and a suitable cable:
 
diff --git a/trac2md.py b/trac2md.py
index 6645bc7..0804608 100755
--- a/trac2md.py
+++ b/trac2md.py
@@ -15,7 +15,7 @@ from datetime import datetime
 from urllib.parse import quote
 
 wikilink_1_pattern = re.compile("\[\[(http.*)\]\]|\[(http.*)\]")
-wikilink_2_pattern = re.compile("\[\[(?:wiki:)?([a-zA-Z0-9_]+)\]\]|\[wiki:([a-zA-Z0-9_]+)\]")
+wikilink_2_pattern = re.compile("\[\[(?:wiki:)?([a-zA-Z0-9_]+)\]\]|\[wiki:(.+)\]")
 strikethrough_pattern = re.compile("~~(.*)~~")
 camelcase_pattern = re.compile("!(\w+)")
 image_pattern = re.compile("\[\[Image\((.*)\)\]\]")
@@ -95,7 +95,13 @@ def convert_wikilinks_2(line):
         if text.lower() == "pageoutline":
             mdlink = ""
         else:
-            mdlink = "[{0}]({0})".format(text)
+            for sep in "| ":
+                if sep in text:
+                    parts = text.split(sep, 1)
+                    break
+            else:
+                parts = [text]
+            mdlink = "[{}]({})".format(parts[-1], parts[0])
         line = line.replace(m.group(0), mdlink)
     return line