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diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md
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@@ -68,7 +68,7 @@ We need to support key wrapping. Some pointers:
# Rough Cut at v0.01 Proof of Concept Feature Set
-As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a [wiki:RoughV1 proposed version 0.01 product] as a proof of concept and a demonstration of the project tools, team, and architecture
+As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a [proposed version 0.01 product](RoughV1) as a proof of concept and a demonstration of the project tools, team, and architecture
@@ -91,10 +91,10 @@ As a proof of concept, to validate as much as possible the assurance of the tool
# Ongoing Development
-* [wiki:SunetInitialDevelopment "SUNET is sponsoring the first two development steps"] currently being done.
-* [wiki:TRNGDevelopment " Investigation and planning of a TRNG with entropy sources"]
-* [wiki:EDAToolchainSurvey" Investigation of possible EDA tools and ways to do open and assured HW development"]
-* [wiki:SideChannel" Collection about side-channel attacks and detection, mitigation methods"]
+* ["SUNET is sponsoring the first two development steps"](SunetInitialDevelopment) currently being done.
+* [" Investigation and planning of a TRNG with entropy sources"](TRNGDevelopment)
+* [Investigation of possible EDA tools and ways to do open and assured HW development"](EDAToolchainSurvey")
+* [Collection about side-channel attacks and detection, mitigation methods"](SideChannel")
# v0.1 Major Sub-Projects
@@ -114,7 +114,7 @@ As a proof of concept, to validate as much as possible the assurance of the tool
* TerasIC C5G Cyclone 5 GX Starter Kit. Includes an Altera C5GX FPGA. This board is used for core, subsystem development and verification. Info, documentation and ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830
-Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hashes on the C5G board"].
+Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](CoretestHashesC5G).
* TerasIC DE0-Nano board. This tiny, USB powered board is used for core development and verification. Info, documentation, resources, ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593
@@ -128,7 +128,7 @@ Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hash
* Research
* Select
-* [wiki:InterconnectStandards "On-chip Interconnect Standards"] to use.
+* ["On-chip Interconnect Standards"](InterconnectStandards) to use.
## Methods and Validation
@@ -190,4 +190,4 @@ Here is a writeup on how to [wiki:CoretestHashesC5G "setup and run coretest_hash
# Future Development
-The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible [wiki:ASICImplementations "ASIC Implementations"].
+The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible ["ASIC Implementations"](ASICImplementations).