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author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
commit | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (patch) | |
tree | ca300cbdbc9b1ca3224441e50375d94c092223e8 /raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md | |
parent | 4ba5e00d5cdd42087a76e379cc39604b2da89ea4 (diff) |
Initial conversion pass
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md')
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diff --git a/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md new file mode 100644 index 0000000..e512c7d --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ftoggle.md @@ -0,0 +1,31 @@ +``` +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +``` + +``` +#!html +<h1>toggle</h1> + +<h2>Introduction</h2> + +<p>This repo contains a simple deign that toggles an ouput pin. The toggle +is in sync with the given sys_clk, but the toggle circuit divides down +the clock. The divisor is build time defined.</p> + +<p>The design is used in the Cryptech FPGA design to observe internal +clock frequencies.</p> + +<h2>Status</h2> + +<p>Has been simulated with Icarus Verilog.</p> +``` + +[[RepositoryIndex(format=table,glob=user/js/toggle)]] + +| Clone `https://git.cryptech.is/user/js/toggle.git` | +|---| |