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module modexpng_dsp_slice_wrapper_generic #
(
AB_INPUT = "DIRECT",
B_REG = 2
)
(
clk,
ce_a1, ce_b1, ce_a2, ce_b2,
ce_m, ce_p, ce_mode,
a, b, p,
inmode, opmode, alumode,
casc_a_in, casc_b_in,
casc_a_out, casc_b_out
);
`include "modexpng_parameters.vh"
`include "modexpng_dsp48e1.vh"
input clk; //
input ce_a1; //
input ce_b1; //
input ce_a2; //
input ce_b2; //
input ce_m; //
input ce_p; //
input ce_mode; //
input [ WORD_EXT_W -1:0] a; //
input [ WORD_W -1:0] b; //
output [ MAC_W -1:0] p; //
input [ DSP48E1_INMODE_W -1:0] inmode; //
input [ DSP48E1_OPMODE_W -1:0] opmode; //
input [DSP48E1_ALUMODE_W -1:0] alumode; //
input [ DSP48E1_A_W -1:0] casc_a_in; //
input [ DSP48E1_B_W -1:0] casc_b_in; //
output [ DSP48E1_A_W -1:0] casc_a_out; //
output [ DSP48E1_B_W -1:0] casc_b_out; //
//
// A Port
//
wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in[WORD_EXT_W-1:0];
reg [WORD_EXT_W -1:0] a_reg1;
reg [WORD_EXT_W -1:0] a_reg2;
assign casc_a_out = a_reg1;
always @(posedge clk) begin
if (ce_a1) a_reg1 <= a_mux;
if (ce_a2) a_reg2 <= a_reg1;
end
//
// B Port
//
wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in[WORD_W-1:0];
reg [WORD_W -1:0] b_reg1;
reg [WORD_W -1:0] b_reg2;
assign casc_b_out = b_reg1;
always @(posedge clk) begin
if (ce_b1) b_reg1 <= b_mux;
if (ce_b2) b_reg2 <= B_REG == 2 ? b_reg1 : b_mux;
end
//
// OPMODE Port
//
reg [DSP48E1_OPMODE_W -1:0] opmode_reg;
always @(posedge clk) begin
if (ce_mode) opmode_reg <= opmode;
end
//
// M, P
//
reg [MAC_W-1:0] m_reg;
reg [MAC_W-1:0] p_reg;
wire [MAC_W-1:0] a_pad = {{MAC_W-WORD_EXT_W{1'b0}}, a_reg2};
wire [MAC_W-1:0] b_pad = {{MAC_W-WORD_W{1'b0}}, b_reg2};
wire [MAC_W-1:0] p_pad = opmode_reg[5] ? p_reg : {MAC_W{1'b0}};
assign p = p_reg;
always @(posedge clk) begin
if (ce_m) m_reg <= a_pad * b_pad;
if (ce_p) p_reg <= m_reg + p_pad;
end
endmodule
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