| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-01-20 | * DSP slices now have two use modes: MULT and ADD/SUB | Pavel V. Shatov (Meister) | |
| * cosmetic rename of Verilog include file | |||
| 2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) | |
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
| faster than the bus clock now. It can be the same, or say four times faster. | |||
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index : user/shatov/modexpng | |
| "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA | git repositories |
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