Redesigned the testbench. Core clock does not necessarily need to be twice

faster than the bus clock now. It can be the same, or say four times faster.

1 files changed, 9 insertions, 0 deletions

diff --git a/rtl/modexpng_dsp_slice_primitive.vh b/rtl/modexpng_dsp_slice_primitive.vh
new file mode 100644
index 0000000..02d9a5d
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_primitive.vh
@@ -0,0 +1,9 @@
+`ifndef MODEXPNG_ENABLE_DEBUG
+
+`define MODEXPNG_DSP_SLICE     modexpng_dsp_slice_wrapper_xilinx
+
+`else
+
+`define MODEXPNG_DSP_SLICE     modexpng_dsp_slice_wrapper_generic
+
+`endif